MPXY8300 datasheet(30/164 Pages) FREESCALE

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MPXY8300 Series

Sensors

Freescale Semiconductor

After any reset, the COP watchdog is enabled. This provides a reliable way to detect code that is not executing as intended. If

the COP watchdog is not used in an application, it can be disabled by clearing the COPE bit in the write-once SOPT1 register.

Even if the application will use the reset default settings in COPE, COPCLKS and COPT0:2, the user should still write to write-

once SOPT1 during reset initialization to lock in the settings. That way, they cannot be changed accidentally if the application

program gets lost.

The write to SRS that services (clears) the COP timer should not be placed in an interrupt service routine (ISR) because the ISR

could continue to be executed periodically even if the main application program fails.

When the MCU is in active background debug mode, the COP watchdog is temporarily disabled.

5.4

Interrupts

Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore

the CPU status so processing resumes where it left off before the interrupt. Other than the software interrupt (SWI), which is a

program instruction, interrupts are caused by hardware events. The debug module can also generate an SWI under certain

circumstances.

If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The CPU will not respond

until and unless the local interrupt enable is a logic 1 to enable the interrupt. The I bit in the CCR must be a logic 0 to allow

interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which masks (prevents) all maskable interrupt

sources. The user program initializes the stack pointer and performs other system setup before clearing the I bit to allow the CPU

to respond to interrupts. When the CPU receives a qualified interrupt request, it completes the current instruction before

responding to the interrupt. The interrupt sequence follows the same cycle-by-cycle sequence as the SWI instruction and consists

of:

•

Saving the CPU registers on the stack

•

Setting the I bit in the CCR to mask further interrupts

•

Fetching the interrupt vector for the highest-priority interrupt that is currently pending

•

Filling the instruction queue with the first three bytes of program information starting from the address fetched from the

interrupt vector locations

Table 5-1 COP Watchdog Time-out Period

COPCLKS

COPT

Clock

Source

COP

Overflow

Count

COP Overflow Time

(msec, nominal)

LFO

128

LFO

256

LFO

512

LFO

210

1024

LFO

211

2048

LFO

211

2048

BUSCLKS1:0

1:1 (0.5 MHz)

1:0 (1 MHz)

0:1 (2 MHz)

0:0 (4MHz)

Bus Clock

213

16.384

8.192

4.096

2.048

Bus Clock

214

32.768

16.384

8.192

4.096

Bus Clock

215

65.536

32.768

16.384

8.192

Bus Clock

216

131.072

65.536

32.768

16.384

Bus Clock

217

262.144

131.072

65.536

32.768

Bus Clock

218

524.288

262.144

131.072

65.536

Bus Clock

219

1048.576

524.288

262.144

131.072

Bus Clock

219

1048.576

524.288

262.144

131.072

MPXY8300 Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

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