MPXY8300 datasheet(29/164 Pages) FREESCALE

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MPXY8300 Series

Sensors

Freescale Semiconductor

SECTION 5 RESET, INTERRUPTS AND SYSTEM CONFIGURATION

This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MPXY8300

Series. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this product

specification. This section gathers basic information about all reset and interrupt sources in one place for easy reference. A few

reset and interrupt sources, including the computer operating properly (COP) watchdog and real-time interrupt (RTI), are not part

of on-chip peripheral systems, but are part of the system control logic.

5.1

Features

Reset and interrupt features include:

•

Multiple sources of reset for flexible system configuration and reliable operation

•

Temperature sensor and temperature restart wake-up

•

Reset status register (SRS) to indicate source of most recent reset

•

Separate interrupt vectors for each module (reduces polling overhead)

5.2

MCU Reset

Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset, most control and status

registers are forced to initial values and the program counter is loaded from the reset vector ($DFFE:$DFFF). On-chip peripheral

modules are disabled and any I/O pins are initially configured as general-purpose high-impedance inputs with any pull-up devices

disabled. The I bit in the condition code register (CCR) is set to block maskable interrupts so the user program has a chance to

initialize the stack pointer (SP) and system control settings. The SP is forced to $00FF at reset.

The device has seven sources for reset:

•

Power-on reset (POR)

•

Low-voltage detect (LVD)

•

Computer operating properly (COP) timer

•

Periodic hardware reset (PRST)

•

Illegal opcode detect

•

Illegal address detect

•

Background debug forced reset

Each of these sources has an associated bit in the system reset status register with the exception of the background debug forced

reset and the periodic hardware reset, PRST, that is indicated by the PRF bit in the PWUCS1 register.

5.3

Computer Operating Properly (COP) Watchdog

The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a

system reset from the COP watchdog (when it is enabled), application software must reset the COP timer periodically. If the

application program gets lost and fails to reset the COP before it times out, a system reset is generated to force the system back

to a known starting point. The COP watchdog is enabled by the COPE bit in SOPT1 register. The COP timer is reset by writing

any value to the address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this

address is decoded and sends a reset signal to the COP timer.

The time-out period can be selected by the COPCLKS and the COPT0:2 bits as shown in Table 5-1. The COPCLKS bit selects

either the LFO or the CPU bus clock as the clocking source and the COPT0:2 bits select the clock count required for a time-out.

The tolerances of these time-out periods is dependent on the selected clock source (LFO or HFO).

MPXY8300 Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc

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