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DSP56364P Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc

Part # DSP56364P
Description  24-Bit Audio Digital Signal Processor
PDF  148 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56364P Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc

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Overview
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
1-3
1.1
Features
1.1.1
Digital Signal Processing Core
•
100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V.
•
Object Code Compatible with the 56000 core.
•
Data ALU with a 24
× 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic
support.
•
Program Control with position independent code support and instruction cache support.
•
Six-channel DMA controller.
•
PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors
(1 to 16) and power saving clock divider (2i: i = 0 to 7). Reduces clock noise.
•
Internal address tracing support and OnCE
™ for Hardware/Software debugging.
•
JTAG port.
•
Very low-power CMOS design, fully static design with operating frequencies down to DC.
•
STOP and WAIT low-power standby modes.
1.1.2
On-Chip Memory Configuration
•
1.5K
× 24 Bit Y-Data RAM.
•1K
× 24 Bit X-Data RAM.
•8K
× 24 Bit Program ROM.
•
0.5K
× 24 Bit Program RAM and 192 × 24 Bit Bootstrap ROM.
•
0.75K
× 24 Bit from Y Data RAM can be switched to Program RAM resulting in up to 1.25K × 24
Bit of Program RAM.
1.1.3
Off-Chip Memory Expansion
•
External Memory Expansion Port with 8-bit data bus.
•
Off-chip expansion up to 2
× 16M × 8-bit word of Data/Program memory when using DRAM.
•
Off-chip expansion up to 2
× 256k × 8-bit word of Data/Program memory when using SRAM.
•
Simultaneous glueless interface to SRAM and DRAM.
1.1.4
Peripheral Modules
•
Enhanced Serial Audio Interface (ESAI): 6 serial lines, 4 selectable as receive or transmit and 2
transmit only, master or slave. I2S, Sony, AC97, network and other programmable protocols.
Unused pins of ESAI may be used as GPIO lines.
•
Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16 and
24-bit words.
•
Four dedicated GPIO lines.



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