DSP56364P datasheet(9/148 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

2-5

2.5.2

External Data Bus

2.5.3

External Bus Control

Table 2-6 External Data Bus Signals

Signal

Name

Type

State During

Reset

Signal Description

D0–D7

Input/

Output

Tri-stated

Data Bus—D0–D7 are active-high, bidirectional input/outputs that provide the

bidirectional data bus for external program and data memory accesses. D0–D7 are

tri-stated during hardware reset and when the DSP is in the stop or wait low-power

standby mode.

Table 2-7 External Bus Control Signals

Signal Name

Type

State During

Reset

Signal Description

AA0–AA1/

RAS0–RAS1

Output

Tri-stated

Address Attribute or Row Address Strobe—When defined as AA, these signals

can be used as chip selects or additional address lines. When defined as

RAS,

these signals can be used as

RAS for DRAM interface. These signals are

tri-stateable outputs with programmable polarity. These signals are tri-stated during

hardware reset and when the DSP is in the stop or wait low-power standby mode.

CAS

Output

Tri-stated

Column Address Strobe—

CAS is an active-low output used by DRAM to strobe

the column address. This signal is tri-stated during hardware reset and when the

DSP is in the stop or wait low-power standby mode.

Output

Tri-stated

Read Enable—

RD is an active-low output that is asserted to read external memory

on the data bus. This signal is tri-stated during hardware reset and when the DSP

is in the stop or wait low-power standby mode.

Output

Tri-stated

Write Enable—

WR is an active-low output that is asserted to write external

memory on the data bus. This signal is tri-stated during hardware reset and when

the DSP is in the stop or wait low-power standby mode.

Input

Ignored Input

Transfer Acknowledge—If there is no external bus activity, the

TA input is ignored.

The

TA input is a data transfer acknowledge (DTACK) function that can extend an

external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be

added to the wait states inserted by the BCR by keeping

TA deasserted. In typical

operation,

TA is deasserted at the start of a bus cycle, is asserted to enable

completion of the bus cycle, and is deasserted before the next bus cycle. The

current bus cycle completes one clock period after

TA is asserted synchronous to

the internal system clock. The number of wait states is determined by the

TA input

or by the bus control register (BCR), whichever is longer. The BCR can be used to

set the minimum number of wait states in external bus cycles.

In order to use the TA functionality, the BCR must be programmed to at least one

wait state. A zero wait state access cannot be extended by TA deassertion,

otherwise improper operation may result.

TA can operate synchronously or

asynchronously, depending on the setting of the TAS bit in the operating mode

TA functionality may not be used while performing DRAM type accesses, otherwise

improper operation may result.

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