M58LT256JST datasheet(84/106 Pages) STMICROELECTRONICS

84 / 106 page

Common Flash Interface

M58LT256JST, M58LT256JSB

84/106

The variable P is a pointer which is defined at CFI offset 015h.

Bank regions. There are two bank regions, see Tables 29 to 34.

Although the device supports Page Read mode, this is not described in the datasheet as its use is not

advantageous in a multiplexed device.

(P+30)h = 13Ah

02h

(P+30)h = 13Ah

02h

Bank region 1 (Erase Block type 1): bits per cell,

internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

Bits 5-7: reserved

(P+31)h = 13Bh

03h

(P+31)h = 13Bh

03h

Bank region 1 (Erase Block type 1): page mode

and synchronous mode capabilities

Bit 0: page-mode reads permitted

Bit 1: synchronous reads permitted

Bit 2: synchronous writes permitted

Bits 3-7: reserved

(P+32)h = 13Ch

0Eh

Bank region 1 Erase Block type 2 information

Bits 0-15: n+1 = number of identical-sized

erase blocks

Bits 16-31: n × 256 = number of bytes in erase

block region

(P+33)h = 13Dh

00h

(P+34)h = 13Eh

00h

(P+35)h = 13Fh

02h

(P+36)h = 140h

64h

Bank region 1 (Erase Block type 2)

Minimum block erase cycles × 1000

(P+37)h = 141h

00h

(P+38)h = 142h

02h

Bank regions 1 (Erase Block Type 2): bits per cell,

internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

Bits 5-7: reserved

(P+39)h = 143h

03h

Bank region 1 (Erase Block Type 2): page mode

and synchronous mode capabilities

Bit 0: page-mode reads permitted

Bit 1: synchronous reads permitted

Bit 2: synchronous writes permitted

Bits 3-7: reserved

Table 43.

Bank and Erase block region 1 information (continued)

M58LT256JST

M58LT256JSB

Description

Offset

Data

Offset

Data

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