M58LT256JST datasheet(85/106 Pages) STMICROELECTRONICS

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M58LT256JST, M58LT256JSB

Common Flash Interface

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Table 44.

Bank and Erase block region 2 information

M58LT256JST

M58LT256JSB

Description

Offset

Data

Offset

Data

(P+32)h = 13Ch

01h

(P+3A)h = 144h

0Fh

Number of identical banks within bank region 2

(P+33)h = 13Dh

00h

(P+3B)h = 145h

00h

(P+34)h = 13Eh

11h

(P+3C)h = 146h

11h

Number of program or erase operations allowed in

bank region 2:

Bits 0-3: number of simultaneous program

operations

Bits 4-7: number of simultaneous erase operations

(P+35)h = 13Fh

00h

(P+3D)h = 147h

00h

Number of program or erase operations allowed in

other banks while a bank in this region is

programming

Bits 0-3: number of simultaneous program

operations

Bits 4-7: number of simultaneous erase operations

(P+36)h = 140h

00h

(P+3E)h = 148h

00h

Number of program or erase operations allowed in

other banks while a bank in this region is erasing

Bits 0-3: number of simultaneous program

operations

Bits 4-7: number of simultaneous erase operations

(P+37)h = 141h

02h

(P+3F)h = 149h

01h

Types of erase block regions in bank region 2

n = number of erase block regions with contiguous

same-size erase blocks.

Symmetrically blocked banks have one blocking

region.(2)

(P+38)h = 142h

0Eh

(P+40)h = 14Ah

0Fh Bank region 2 Erase Block type 1 information

Bits 0-15: n+1 = number of identical-sized erase

blocks

Bits 16-31: n × 256 = number of bytes in erase

block region

(P+39)h = 143h

00h

(P+41)h = 14Bh

00h

(P+3A)h = 144h

00h

(P+42)h = 14Ch

00h

(P+3B)h = 145h

02h

(P+43)h = 14Dh

02h

(P+3C)h = 146h

64h

(P+44)h = 14Eh

64h Bank region 2 (Erase Block type 1)

Minimum block erase cycles × 1000

(P+3D)h = 147h

00h

(P+45)h = 14Fh

00h

(P+3E)h = 148h

02h

(P+46)h = 150h

02h

Bank region 2 (Erase Block type 1): bits per cell,

internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

Bits 5-7: reserved

(P+3F)h = 149h

03h

(P+47)h = 151h

03h

Bank region 2 (Erase Block type 1): page mode

and synchronous mode capabilities (defined in

Table 41)

Bit 0: page-mode reads permitted

Bit 1: synchronous reads permitted

Bit 2: synchronous writes permitted

Bits 3-7: reserved

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