M58LT256JST datasheet(86/106 Pages) STMICROELECTRONICS

86 / 106 page

Common Flash Interface

M58LT256JST, M58LT256JSB

86/106

The variable P is a pointer which is defined at CFI offset 015h.

Bank regions. There are two bank regions, see Tables 29 to 34.

Although the device supports Page Read mode, this is not described in the datasheet as its use is not

advantageous in a multiplexed device.

(P+40)h = 14Ah

03h

Bank region 2 Erase Block type 2 information

Bits 0-15: n+1 = number of identical-sized erase

blocks

Bits 16-31: n × 256 = number of bytes in erase

block region

(P+41)h = 14Bh

00h

(P+42)h = 14Ch

80h

(P+43)h = 14Dh

00h

(P+44)h = 14Eh

64h

Bank region 2 (Erase Block type 2)

Minimum block erase cycles × 1000

(P+45)h = 14Fh

00h

(P+46)h = 150h

02h

Bank region 2 (Erase Block Type 2): bits per cell,

internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

Bits 5-7: reserved

(P+47)h = 151h

03h

Bank region 2 (Erase Block type 2): page mode

and synchronous mode capabilities (defined in

Table 41)

Bit 0: page-mode reads permitted

Bit 1: synchronous reads permitted

Bit 2: synchronous writes permitted

Bits 3-7: reserved

(P+48)h = 152h

Feature space definitions

(P+49)h = 153h

(P+43)h = 153h

Reserved

Table 44.

Bank and Erase block region 2 information (continued)

M58LT256JST

M58LT256JSB

Description

Offset

Data

Offset

Data

M58LT256JST Datasheet(PDF) 86 Page - STMicroelectronics

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