IBIS4-1300
Document Number: 38-05707 Rev. *B
Page 24 of 37
• The next row (=line) is selected after the falling edge of
CLK_YR and CLK_YL,
• The column amplifiers receive the signals on the pixels array
columns buses when SHY is low (transparent).
• The SIN pulse (high) forces the column amplifiers in an
“offset nulling" state.
• After 3 us, the column amplifiers have reached offset-free
equilibrium, and the SIN pulse is brought low again. The
pixel's signal level is thus stored in the column amplifier.
• After that the pixels in the selected row (line) are be reset
(first pulse on RESET).
• Consequently the reset level is frozen in the column
amplifiers when SHY goes high. Both signal level and reset
level have now been applied to the column amplifiers. The
sample hold (SHY) guarantees that this information will not
change anymore during readout of the line.
• Now, the row is ready for readout. A pulse on SYNC_X must
be given to start the row readout. SYNC_X initiates the
X-direction scanning register. The scanning itself is
controlled by CLOCK_X.
• During the beginning of the row readout, or possibly before,
the RESET pulse for the electronic shutter (ES) must be
given, if the ES is used. This is a pulse on RESET together
with a high level on L/R. If the ES is not used, L/R remains
low and the second RESET pulse is not generated.
During some or the entire row blanking times, the output
amplifier can be calibrated.
If the slow calibration method is used, pulse the 'CALIB_S' pin
once per line. The calibration happens on the rising edge of
the pulse.
If the fast calibration is used, the 'CALIB_F' should be pulsed
during the row blanking time of the first row only. This
calibration happens during the time that the pulse is high.
During this calibration, the input applied to the amplifier must
be the dark reference, which can either be the built-in electrical
dark reference, or an external dark reference on the pin
EXTIN.
Figure 19. Pulse on 'CALIB_F'& 'UNITYGAIN' to be given once per frame, or on CALIB_S once per line
The X-direction shift register
The X shift register behaves like the Y shift registers.
The sequence if initiated by SYNC_X, which should occur
when CLOCK_X is high. As CLOCK_X is halted during the
blanking time, the SYNC_X pulse could occur anywhere, and
be taken equal to some other pulse (e.g. CLOCK_Y).
The first real (dummy) pixel is read out after the 3rd falling
edge on the clock. Dummy pixels are perfectly operational
pixels, but are added to shield the "real" pixels from the cross
talk of the periphery.
Signal applied to
input of amplifier
Calib_s
or
Calib_f
500ns (calib_f)
"Dark"
reference
100ns
100ns (calib_s)
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