30 / 37 page
IBIS4-1300
Document Number: 38-05707 Rev. *B
Page 30 of 37
29
clk_x
D
I
Shifts on falling edge
clock X shift register
30
shy
D
I
Column parallel track and hold
1 = hold; 0 = track
31
dccon
A
I
control voltage for DC reference
generation
Connect to GND (default)
32
dcref
A
O
reference voltage
Should be +/- 1.2 V, depends on dccon
33
gnd
A
G
34
vdd
A
P
35
sin
D
I
Column amplifier calibration signal
1 = calibrate, see timing diagram
36
sync_y\l
D
I
0 = start left shift register
low active (0=sync)
37
clk_yl
D
I
clock left shift register
Shifts on falling edge
38
eos_yl\
D
O
low 1st clk_yl pulse after last row
Active low
39
bitinvert
D
I
High active, 1 = invert bits
inverts ADC output bits
40
select
D
I
High active
selects row indicated by left/right shift
register
41
reset
D
I
High active
resets row indicated by left/right shift
register
42
d9
W
O
MSB
ADC output
43
d8
W
O
44
d7
W
O
45
d6
W
O
46
d5
W
O
47
d4
W
O
48
d3
W
O
49
d2
W
O
50
d1
W
O
51
d0
W
O
LSB
52
gnd
A
G
53
vdd
A
P
+ 5 V DC
54
gnd_ab
A
G
Anti-blooming drain voltage
GND or +1V for improved anti-blooming
55
vdd_array
A
P
+ 5 V DC
Pixel power supply
56
vdd_dig
D
P
+ 5 V DC
ADC digital power supply
57
gnd_dig
D
G
ADC ground of digital circuits
58
vdd_an
A
P
+ 5 V DC
ADC analog power supply
59
vdd_resetl
A
P
5 V DC default
(5.5 V for large output swing)
4…4.5 V for double slope mode
VDD for reset by left shift register
60
gnd_an
A
G
ADC ground of analog circuits
61
vhigh_adc
A
I
+ 4 V DC
High ADC reference voltage
No.
Name
Type
I/O
Description
Signal
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