PIC18F6X2X datasheet(115/386 Pages) MICROCHIP

115 / 386 page

 2003 Microchip Technology Inc.

Advance Information

DS39612A-page 113

PIC18F6X2X/8X2X

10.4

PORTD, TRISD and LATD

Registers

PORTD is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISD bit (= 0)

will make the corresponding PORTD pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

PORTD.

PORTD is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually configurable as an input or

output.

PORTD is multiplexed with the system bus as the

external memory interface; I/O port functions are only

available when the system bus is disabled by setting

the

EBDIS

bit

the

MEMCOM

(MEMCON<7>). When operating as the external

memory interface, PORTD is the low order byte of the

multiplexed address/data bus (AD7:AD0).

PORTD can also be configured as an 8-bit wide

microprocessor port (Parallel Slave Port) by setting

control bit PSPMODE (TRISE<4>). In this mode, the

input buffers are TTL. See Section 10.10 for additional

information on the Parallel Slave Port (PSP).

EXAMPLE 10-4:

INITIALIZING PORTD

FIGURE 10-9:

PORTD BLOCK DIAGRAM

IN I/O PORT MODE

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

CLRF

PORTD

; Initialize PORTD by

; clearing output

; data latches

CLRF

LATD

; Alternate method

; to clear output

; data latches

MOVLW 0xCF

; Value used to

; initialize data

; direction

MOVWF TRISD

; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

Data

Bus

WR LATD

WR TRISD

RD PORTD

Data Latch

TRIS Latch

RD TRISD

Schmitt

Trigger

Input

Buffer

I/O pin(1)

RD LATD

PORTD

Note 1:

I/O pins have diode protection to VDD and VSS.

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