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PIC18F6X2X Datasheet(PDF) 125 Page - Microchip Technology |
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PIC18F6X2X Datasheet(HTML) 125 Page - Microchip Technology |
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125 / 386 page ![]() 2003 Microchip Technology Inc. Advance Information DS39612A-page 123 PIC18F6X2X/8X2X FIGURE 10-17: MCLR/VPP/RG5 PIN BLOCK DIAGRAM TABLE 10-13: PORTG FUNCTIONS TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG MCLR/VPP/RG5 Data Bus RD PORTA RD LATA Schmitt Trigger MCLRE RD TRISA QD EN Latch Filter Low Level MCLR Detect High Voltage Detect Internal MCLR HV Name Bit# Buffer Type Function RG0/CCP3/P3A bit 0 ST Input/output port pin, Capture3 input/Compare3 output/PWM3 output, or Enhanced PWM3 output P3A. RG1/TX2/CK2 bit 1 ST Input/output port pin, Addressable USART2 Asynchronous Transmit, or Addressable USART2 Synchronous Clock. RG2/RX2/DT2 bit 2 ST Input/output port pin, Addressable USART2 Asynchronous Receive, or Addressable USART2 Synchronous Data. RG3/CCP4/P3D bit 3 ST Input/output port pin, Capture4 input/Compare4 output/PWM4 output, or Enhanced PWM3 output P3D. RG4/CCP5/P1D bit 4 ST Input/output port pin, Capture5 input/Compare5 output/PWM5 output, or Enhanced PWM1 output P1D. MCLR/VPP/RG5 bit 5 ST Master Clear input or programming voltage input (if MCLR is enabled). Input only port pin or programming voltage input (if MCLR is disabled). Legend: ST = Schmitt Trigger input Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS PORTG — —RG5(1) Read PORTG pin/Write PORTG Data Latch --0x xxxx --0u uuuu LATG — — — LATG Data Output Register ---x xxxx ---u uuuu TRISG — — — Data Direction Control Register for PORTG ---1 1111 ---1 1111 Legend: x = unknown, u = unchanged Note 1: RG5 is available as an input only when MCLR is disabled. |
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