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PIC18F6X2X Datasheet(PDF) 197 Page - Microchip Technology |
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PIC18F6X2X Datasheet(HTML) 197 Page - Microchip Technology |
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197 / 386 page  2003 Microchip Technology Inc. Advance Information DS39612A-page 195 PIC18F6X2X/8X2X 18.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, setting the CKP bit will not assert the SCL output low until the SCL output is already sam- pled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set, and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 18-12). FIGURE 18-12: CLOCK SYNCHRONIZATION TIMING SDA SCL DX-1 DX WR Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SSPCON CKP Master device deasserts clock Master device asserts clock |
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