PIC18F6X2X datasheet(201/386 Pages) MICROCHIP

201 / 386 page

 2003 Microchip Technology Inc.

Advance Information

DS39612A-page 199

PIC18F6X2X/8X2X

18.4.6

MASTER MODE

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON1 and by setting the

SSPEN bit. In Master mode, the SCL and SDA lines

are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the START and STOP

conditions. The STOP (P) and START (S) bits are

cleared from a RESET or when the MSSP module is

disabled. Control of the I2C bus may be taken when the

P bit is set or the bus is IDLE, with both the S and P bits

clear.

In Firmware Controlled Master mode, user code con-

ducts all I2C bus operations based on START and

STOP bit conditions.

Once Master mode is enabled, the user has six

options.

Assert a START condition on SDA and SCL.

Assert a Repeated START condition on SDA

and SCL.

Write

the

SSPBUF

initiating

transmission of data/address.

Configure the I2C port to receive data.

Generate an Acknowledge condition at the end

of a received byte of data.

Generate a STOP condition on SDA and SCL.

The following events will cause SSP interrupt flag bit,

SSPIF, to be set (SSP interrupt, if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeated START

FIGURE 18-16:

MSSP BLOCK DIAGRAM (I2C MASTER MODE)

Note:

The MSSP module, when configured in

I2C Master mode, does not allow queueing

of events. For instance, the user is not

allowed to initiate a START condition and

immediately write the SSPBUF register to

initiate transmission before the START

condition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

Read

Write

SSPSR

START bit, STOP bit,

START bit Detect

SSPBUF

Internal

Data Bus

Set/Reset, S, P, WCOL (SSPSTAT)

Shift

Clock

MSb

LSb

SDA

Acknowledge

Generate

STOP bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

SCL

SCL In

Bus Collision

SDA In

SSPADD<6:0>

Baud

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

Rate

Generator

SSPM3:SSPM0

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