PPC440EP datasheet(50/84 Pages) AMCC

50 / 84 page

AMCC Proprietary

440EP – PPC440EP Embedded Processor

Revision 1.26 – April 25, 2007

Data Sheet

Table 6. Signal Functional Description (Sheet 1 of 9)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PCI Interface

PCIAD00:31

Address/Data bus (bidirectional).

I/O

3.3V PCI

PCIC0:3/BE0:3

PCI Command/Byte Enables

I/O

3.3V PCI

PCIClk

Provides timing to the PCI interface for PCI transactions.

3.3V PCI

PCIDevSel

Indicates the driving device has decoded its address as the

target of the current access.

I/O

3.3V PCI

PCIFrame

Driven by the current master to indicate beginning and

duration of an access.

I/O

3.3V PCI

PCIGnt0/Req

Indicates that the specified agent is granted access to the bus.

When the internal arbiter is enabled, output is PCIGnt0. When

the internal arbiter is disabled, output is Req.

3.3V PCI

PCIGnt1:5

Indicates that the specified agent is granted access to the bus.

Used only when internal PCI arbiter enabled.

3.3V PCI

PCIIDSel

Used as a chip select during configuration read and write

transactions.

3.3V PCI

PCIINT

Level sensitive PCI interrupt.

3.3V PCI

PCIIRDY

Indicates initiating agent’s ability to complete the current data

phase of the transaction.

I/O

3.3V PCI

PCIPar

Even parity.

I/O

3.3V PCI

PCIPErr

Reports data parity errors during all PCI transactions except a

Special Cycle.

I/O

3.3V PCI

PCIReq0/Gnt

Indicates to the PCI arbiter that the specified agent wishes to

use the bus. When the internal arbiter is enabled, input is

PCIReq0. When internal arbiter is disabled, input is Gnt.

3.3V PCI

PCIReq1:5

An indication to the PCI arbiter that the specified agent wishes

to use the bus. Used only when internal PCI arbiter enabled.

3.3V PCI

PCIReset

Brings PCI device registers and logic to a consistent state.

3.3V PCI

PCISErr

Reports address parity errors, data parity errors on the Special

Cycle command, or other catastrophic system errors.

I/O

3.3V PCI

PCIStop

Current target is requesting the master to stop the current

transaction.

I/O

3.3V PCI

PCITRDY

Target agent’s ability to complete the current data phase of the

transaction.

I/O

3.3V PCI

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