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PPC440EP Datasheet(PDF) 66 Page - Applied Micro Circuits Corporation |
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PPC440EP Datasheet(HTML) 66 Page - Applied Micro Circuits Corporation |
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66 / 84 page  66 AMCC Proprietary 440EP – PPC440EP Embedded Processor Revision 1.26 – April 25, 2007 Data Sheet Figure 5. Input Setup and Hold Waveform Figure 6. Output Delay and Float Timing Waveform TmrClk input frequency – 100 MHz TmrClk period 10 – ns TmrClk input high time 40% of nominal period 60% of nominal period ns TmrClk input low time 40% of nominal period 60% of nominal period ns Notes: 1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maxi- mum OPB clock frequency is 66.66 MHz. Table 15. Peripheral Interface Clock Timings (Continued) Parameter Min Max Units Notes Clock TIS TIH min min Inputs Valid Valid Clock Outputs Valid TOH min TOVmax TOVmax TOH min TOVmax TOH min Float (High-Z) High (Drive) Low (Drive) |
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