PPC440GP-3CC466C datasheet(48/83 Pages) AMCC

48 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

Signal Functional Description (Sheet 1 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V, 10kΩ to 5V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PCI-X Interface

PCIXAD00:63

Address/Data bus (bidirectional).

I/O

3.3V PCI

PCIXC0:7[BE0:7]

PCI-X Command[Byte Enables]

I/O

3.3V PCI

PCIXCap

Capable of PCI-X operation.

5V tolerant

3.3V LVTTL

PCIX133Cap

PCI-X devices are 133 MHz capable.

3.3V PCI

PCIXClk

Provides timing to the PCI interface for PCI transactions.

Note:If the PCI-X interface is not being used, drive this pin with a

3.3V clock signal at a frequency between 1 and 66MHz

3.3V PCI

PCIXDevSel

Indicates the driving device has decoded its address as the target

of the current access.

I/O

3.3V PCI

PCIXFrame

Driven by the current master to indicate beginning and duration of

an access.

I/O

3.3V PCI

PCIXGnt0

Indicates that the specified agent is granted access to the bus.

I/O

3.3V PCI

PCIXGnt1

Indicates that the specified agent is granted access to the bus.

I/O

3.3V PCI

PCIXGnt2:5

Indicates that the specified agent is granted access to the bus.

3.3V PCI

PCIXIDSel

Used as a chip select during configuration read and write

transactions.

3.3V PCI

PCIXINT

Level sensitive PCI interrupt.

3.3V PCI

PCIXIRDY

Indicates initiating agent’s ability to complete the current data

phase of the transaction.

I/O

3.3V PCI

PCIXM66En

Capable of 66MHz operation.

5V tolerant

3.3V LVTTL

PCIXParHigh

Even parity across PCIAD32:63 and PCIXC0:3[BE4:7].

I/O

3.3V PCI

PCIXParLow

Even parity across PCIAD0:31 and PCIXC0:3[BE0:3].

I/O

3.3V PCI

PCIXPErr

Reports data parity errors during all PCI transactions except a

Special Cycle.

I/O

3.3V PCI

PCIXReq0

An indication to the PCI-X arbiter that the specified agent wishes

to use the bus.

I/O

3.3V PCI

PCIXReq1:5

An indication to the PCI-X arbiter that the specified agent wishes

to use the bus.

3.3V PCI

PCIXReq64

Asserted by the current bus master, indicating a 64-bit transfer.

I/O

3.3V PCI

PCIXAck64

Indicates the target can transfer data using 64 bits.

I/O

3.3V PCI

PCIXReset

Brings PCI device registers and logic to a consistent state.

3.3V PCI

PCIXSErr

Reports address parity errors, data parity errors on the Special

Cycle command, or other catastrophic system errors.

I/O

3.3V PCI

PCIXStop

Indicates the current target is requesting the master to stop the

current transaction.

I/O

3.3V PCI

PCIXTRDY

Indicates the target agent’s ability to complete the current data

phase of the transaction.

I/O

3.3V PCI

PPC440GP-3CC466C Datasheet(PDF) 48 Page - Applied Micro Circuits Corporation

PPC440GP-3CC466C Datasheet(HTML) 48 Page - Applied Micro Circuits Corporation

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