PPC440GP-3CC466C datasheet(62/83 Pages) AMCC

62 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

Peripheral Interface Clock Timings

Parameter

Min

Max

Units

Notes

PCIXClk input frequency (asynchronous mode)

–

133.33

MHz

PCIXClk period (asynchronous mode)

7.5

–

PCIXClk input high time

40% of nominal period

60% of nominal period

PCIXClk input low time

40% of nominal period

60% of nominal period

EMCMDClk output frequency

–

2.5

MHz

EMCMDClk period

400

–

EMCMDClk output high time

160

–

EMCMDClk output low time

160

–

EMCTxClk input frequency MII(RMII)

2.5(5)

25(50)

MHz

EMCTxClk period MII(RMII)

40(20)

400(200)

EMCTxClk input high time

35% of nominal period

–

EMCTxClk input low time

35% of nominal period

–

EMCRxClk input frequency MII(RMII)

2.5(5)

25(50)

MHz

EMCRxClk period MII(RMII)

40(20)

400(200)

EMCRxClk input high time

35% of nominal period

–

EMCRxClk input low time

35% of nominal period

–

EMCRefClk input frequency

–

MHz

EMCRefClk period

EMCRefClk input high time

45% of nominal period

55% of nominal period

EMCRefClk input low time

45% of nominal period

55% of nominal period

PerClk output frequency (for ext. master or sync. slaves)

–

66.66

MHz

PerClk period

–

PerClk output high time

50% of nominal period

66% of nominal period

PerClk output low time

33% of nominal period

50% of nominal period

UARTSerClk input frequency

–

1000/(2TOPB

1+2ns)

MHz

UARTSerClk period

2TOPB+2

–ns

UARTSerClk input high time

TOPB+1

–ns

UARTSerClk input low time

TOPB+1

–ns

PPC440GP-3CC466C Datasheet(PDF) 62 Page - Applied Micro Circuits Corporation

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