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HYS72T512341HKP Datasheet(PDF) 5 Page - Qimonda AG |
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HYS72T512341HKP Datasheet(HTML) 5 Page - Qimonda AG |
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5 / 32 page ![]() Internet Data Sheet Rev. 1.0, 2006-12 5 11032006-VX0M-M6IH HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules 2 Pin Configuration 2.1 Pin Configuration The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1. TABLE 5 Pin Configuration of RDIMM Pin No. Name Pin Type Buffer Type Function Clock Signals 185 CK0 I SSTL Clock Signal CK0, Complementary Clock Signal CK0 186 CK0 I SSTL 52 CKE0 I SSTL Clock Enables 1:0 Note: 2-Ranks module 171 CKE1 I SSTL NC NC — Not Connected Note: 1-Rank module Control Signals 193 S0 I SSTL Chip Select Rank 3:0 76 S1 I SSTL 220 S2 I SSTL 221 S3 I SSTL 192 RAS I SSTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) 74 CAS I SSTL 73 WE I SSTL 18 RESET ICMOS Register Reset Address Signals 71 BA0 I SSTL Bank Address Bus 1:0 190 BA1 I SSTL 54 BA2 I SSTL Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS NC I SSTL Not Connected Less than 1Gb DDR2 SDRAMS |
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