HYS72T512341HKP datasheet(16/32 Pages) QIMONDA

16 / 32 page

Internet Data Sheet

Rev. 1.0, 2006-12

11032006-VX0M-M6IH

HYS72T512341H[H/J/K]P-[3.7/5]-B

Registered DDR2 SDRAM Modules

3.4

IDD Specifications and Conditions

List of tables defining

DD Specifications and Conditions.

• Table 13 “IDD Measurement Conditions” on Page 16

• Table 14 “Definitions for IDD” on Page 17

• Table 15 “IDD Specification for HYS72T512341H[HJ/K]P–[3.7/5]–B” on Page 18

TABLE 13

DD Measurement Conditions

Parameter

Symbol Note

1)2)3)4)5)

Operating Current 0

One bank Active - Precharge;

CK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between

valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.

DD0

Operating Current 1

One bank Active - Read - Precharge;

OUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN,

RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and

control inputs are SWITCHING, Databus inputs are SWITCHING.

DD1

Precharge Standby Current

All banks idle; CS is HIGH; CKE is HIGH;

CK = tCK.MIN; Other control and address inputs are SWITCHING,

Databus inputs are SWITCHING.

DD2N

Precharge Power-Down Current

Other control and address inputs are STABLE, Data bus inputs are FLOATING.

DD2P

Precharge Quiet Standby Current

All banks idle; CS is HIGH; CKE is HIGH;

CK = tCK.MIN; Other control and address inputs are STABLE,

Data bus inputs are FLOATING.

DD2Q

Active Standby Current

Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;

RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are

SWITCHING; Data Bus inputs are SWITCHING;

OUT = 0 mA.

DD3N

Active Power-Down Current

All banks open;

CK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs

are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);

DD3P(0)

Active Power-Down Current

All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs

are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);

DD3P(1)

Operating Current - Burst Read

All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX;

RP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data

bus inputs are SWITCHING;

OUT = 0mA.

DD4R

Operating Current - Burst Write

All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;

RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are

SWITCHING; Data Bus inputs are SWITCHING;

DD4W

Burst Refresh Current

CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid

commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.

DD5B

HYS72T512341HKP Datasheet(PDF) 16 Page - Qimonda AG

HYS72T512341HKP Datasheet(HTML) 16 Page - Qimonda AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL