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HYS72T512341HKP Datasheet(PDF) 14 Page - Qimonda AG

Part # HYS72T512341HKP
Description  240-Pin Registered DDR2 SDRAM Modules
PDF  32 Pages
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Manufacturer  QIMONDA [Qimonda AG]
Direct Link  http://www.qimonda.com
Logo QIMONDA - Qimonda AG

HYS72T512341HKP Datasheet(HTML) 14 Page - Qimonda AG

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Internet Data Sheet
Rev. 1.0, 2006-12
14
11032006-VX0M-M6IH
HYS72T512341H[H/J/K]P-[3.7/5]-B
Registered DDR2 SDRAM Modules
3.2
D.C. Characteristics
TABLE 10
Operating Conditions
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Values
Unit
Note
Min.
Max.
Operating temperature (ambient)
T
OPR
0+65
°C
DRAM Case Temperature
T
CASE
0+90
°C
1)2)3)4)
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
3) Above 80 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to
t
REFI = 3.9 µs
4) When operating this product in the 85 °C to 95 °C
T
CASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of
I
DD6 by approximately 50%.
Storage Temperature
T
STG
– 50
+100
°C
Barometric Pressure (operating & storage)
PBar
+69
+105
kPa
5)
5) Up to 3000 m.
Operating Humidity (relative)
H
OPR
10
90
%
Parameter
Symbol
Values
Unit
Note
Min.
Typ.
Max.
Device Supply Voltage
V
DD
1.7
1.8
1.9
V
Output Supply Voltage
V
DDQ
1.7
1.8
1.9
V
1)
1) Under all conditions,
V
DDQ must be less than or equal to VDD
Input Reference Voltage
V
REF
0.49
× V
DDQ
0.5
× V
DDQ
0.51
× V
DDQ
V
2)
2) Peak to peak AC noise on
V
REF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ.
SPD Supply Voltage
V
DDSPD
1.7
—
3.6
V
DC Input Logic High
V
IH(DC)
V
REF +0.125
—
V
DDQ +0.3
V
DC Input Logic Low
V
IL (DC)
– 0.30
—
V
REF – 0.125
V
In / Output Leakage Current
I
L
– 5
—
5
µA
3)
3) Input voltage for any connector pin under test of 0 V
≤ V
IN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin



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