ST10F272M datasheet(167/175 Pages) STMICROELECTRONICS

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ST10F272M

Electrical characteristics

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Figure 61.

SSC master timing

The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock

edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading

clock edge is low-to-high transition (SSCPO = 0b).

The bit timing is repeated for all bits to be transmitted or received.

t307p SR

Read data setup time before latch

edge, phase error detection on

(SSCPEN = 1)

37.5

–

2TCL + 12.5

–

t308p SR

Read data hold time after latch

edge, phase error detection on

(SSCPEN = 1)

–

4TCL

–

t307

Read data setup time before latch

edge, phase error detection off

(SSCPEN = 0)

–

2TCL

–

t308

Read data hold time after latch

edge, phase error detection off

(SSCPEN = 0)

0–0

–

When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the

limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only with CPU clock equal to (or lower than) 32 MHz.

Formula for SSC Clock Cycle time: t300 = 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC

baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t300 is 125ns (corresponding to 8Mbaud).

Partially tested, guaranteed by design characterization.

Table 74.

SSC master mode timings (continued)

Symbol

Parameter

Maximum baudrate

6.6 Mbaud(1)

@fCPU = 40 MHz

(<SSCBR> = 0002h)

Variable baudrate

(<SSCBR> = 0001h - FFFFh)

Unit

Min

Max

Min

Max

1st out bit

Last out bit

2nd out bit

(1)

(2)

2nd In bit

1st in bit

Last in bit

SCLK

MTSR

MRST

t308

t307

t308

t307

t305

t300

t301

t302

t304

t303

t306

t305

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