LMH6583

SNOSAP5E – APRIL 2006 – REVISED MARCH 2013

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transition (1 to 0) of the clock signal. All input data is read from the bus on the negative edge of the clock signal.

Once the last valid data has been clocked in, the chip select pin must go high then the clock signal must make at

least one more low to high transition. Otherwise invalid data will be clocked into the chip. The data clocked into

the chip is not transferred to the crosspoint matrix until the CFG pin is pulsed high. This is the case regardless of

the state of the Mode pin. The CFG pin is not dependent on the state of the Chip select pin. If no new data is

clocked into the chip subsequent pulses on the CFG pin will have no effect on device operation.

The programming format of the incoming serial data is selected by the MODE pin. When the mode pin is HIGH

the crosspoint can be programmed one output at a time by entering a string of data that contains the address of

the output that is going to be changed (Addressed Mode). When the mode pin is LOW the crosspoint is in Serial

Mode. In this mode the crosspoint accepts a 40 bit array of data that programs all of the outputs. In both modes

the data fed into the chip does not change the chip operation until the Configure pin is pulsed high. The configure

and mode pins are independent of the chip select pin.

THREE WIRE VS. FOUR WIRE CONTROl

There are two ways to connect the serial data pins. The first way is to control all 4 pins separately, and the

second option is to connect the CFG and the CS pins together for a 3 wire interface. The benefit of the 4 wire

interface is that the chip can be configured independently of the CS pin. This would be an advantage in a system

with multiple crosspoint chips where all of them could be programmed ahead of time and then configured

simultaneously. The 4 wire solution is also helpful in a system that has a free running clock on the CLK pin. In

this case, the CS pin needs to be brought high after the last valid data bit to prevent invalid data from being

clocked into the chip.

The three wire option provides the advantage of one less pin to control at the expense of having less flexibility

with the configure pin. One way around this loss of flexibility would be If the clock signal is generated by an

FPGA or microcontroller where the clock signal can be stopped after the data is clocked in. In this case the Chip

select function is provided by the presence or absence of the clock signal.

SERIAL PROGRAMMING MODE

Serial programming mode is the mode selected by bringing the MODE pin low. In this mode a stream of 40 bits

programs all 8 outputs of the crosspoint. The data is fed to the chip as shown in Table 1 through Table 4 (4

tables are required to show the entire data frame). The table is arranged such that the first bit clocked into the

crosspoint register is labeled bit number 0. The register labeled Load Register in Figure 39 is a shift register. If

the chip select pin is left low after the valid data is shifted into the chip and if the clock signal keeps running then

additional data will be shifted into the register, and the desired data will be shifted out.

Also illustrated is the timing relationships for the digital pins in Figure 40. It is important to note that all the pin

timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS)

must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to

synchronize to allow data to be accepted on the next falling edge. After the final data bit has been clocked in, the

chip select pin must go high, then the clock signal must make at least one more low to high transition. As shown

in Figure 40, the chip select pin state should always occur while the clock signal is low. The configure (CFG) pin

timing is not so critical, but it does need to be kept low until all data has been shifted into the crosspoint registers.

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