1

64

CFG

DOUT

VCC

CLK

OUT7

GND

VEE

GND

OUT6

VCC

BCST

GND

VEE

GND

OUT4

VCC

OUT5

IN15

IN8

VEE

IN9

VCC

IN10

VEE

IN11

VCC

VEE

IN13

VCC

IN14

VEE

IN12

16

32

48

GND

SWITCH

MATRIX

CONFIGURATION

REGISTER

LOAD

REGISTER

DATA OUT

RST

DATA IN

CS

CLK

MODE

BCST

CFG

40

136

LMH6583

SNOSAP5E – APRIL 2006 – REVISED MARCH 2013

www.ti.com

Connection Diagram

Figure 1. 64-Pin Exposed Pad HTQFP

Figure 2. Block Diagram

See Package Number PAP0064A

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2)

ESD Tolerance (3)

Human Body Model

2000V

Machine Model

200V

VS

±6V

IIN (Input Pins)

±20 mA

IOUT

(4)

Input Voltage Range

V− to V+

Maximum Junction Temperature

+150°C

Storage Temperature Range

−65°C to +150°C

Soldering Information

Infrared or Convection (20 sec.)

235°C

Wave Soldering (10 sec.)

260°C

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see ±3.3V Electrical

Characteristics and ±5V Electrical Characteristics.

(2)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3)

Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of

JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

(4)

The maximum output current (IOUT) is determined by device power dissipation limitations.

2

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