PCM1738ESLASH2K datasheet(17/47 Pages) TI2

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AUDIO DATA INTERFACE

AUDIO SERIAL INTERFACE

AUDIO DATA FORMATS AND TIMING

PCM1738

SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007

The audio serial interface for the PCM1738 consists of a 3-wire synchronous serial port. It includes LRCK (pin

4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, used to clock the serial data present on

DATA into the audio interface serial shift register. Serial data is clocked into the PCM1738 on the rising edge of

BCK. LRCK is the serial audio left/right word clock, used to latch serial data into the serial audio interface

internal registers.

LRCK should be synchronous to the system clock. In the event these clocks are not synchronized, the

PCM1738 can compensate for the phase difference internally. If the phase difference between LRCK and SCKI

is greater than six bit clocks (BCK), the synchronization is performed internally. While the synchronization is

processing, the analog output is forced to the bipolar zero level. The synchronization typically occurs in less than

one cycle of LRCK.

Ideally, it is recommended that LRCK and BCK be derived from the system clock input or output, SCKI or

SCKO. The left/right clock (LRCK) is operated at the sampling frequency, fS.

The PCM1738 supports industry-standard audio data formats, including standard right-justified, I2S, and

left-justified. The data formats are shown in Figure 35. Data formats are selected using the format bits, FMT

[2:0], in mode control register 18. The default data format is 16-bit standard. All formats require binary

2s-complement, MSB-first audio data. Figure 36 shows a detailed timing diagram for the serial audio interface.

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