PCM1738ESLASH2K datasheet(38/47 Pages) TI2

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DSD-MODE CONFIGURATION AND FUNCTION CONTROLS

REQUIREMENTS FOR SYSTEM CLOCK

PCM1738

SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007

Configuration for DSD interface mode:

• DFTH = 1 (register 20)

• DME = 1 (register 18)

Table 6 shows the register mapping available in DSD mode.

Table 6. Register Mapping in DSD Mode

B15

B14

B13

B12

B11

B10

W/R

–(1)

–

W/R

–

W/R

–

DMF1

DMF0

DME(2)

–

W/R

–

OPE

CLKD

CLKE

–

W/R

RSV

SRST

MRST

RSV

OS1

OS0

DFTH(2)

RSV

–

(1)

– = function disabled. No operation even if any data is set.

(2)

These bits are required for selection of the DSD mode.

DMF[1:0]

Analog FIR Performance Selection

These bits are available for read/write.

Default value: 00

DMF[1:0]

Analog FIR Performance Select

DSD filter 1 (default)

DSD filter 2

DSD filter 3

DSD filter 4

Plots for the four analog FIR filter responses are shown in the Typical Performance Curves of this

data sheet.

OS[1:0]

Analog FIR Operation Speed Selection

These bits are available for read/write.

Default value: 00

OS[1:0]

Operation Speed Select

fSCKI (default)

Reserved

fSCKI/2

The OS bit in the DSD mode is used to select the operating rate of the analog FIR.

The bit clock (BCK) for DSD mode is required at pin 7 of the PCM1738. The frequency of the bit clock may be N

times the sampling frequency. Generally, N is 64 in DSD applications.

The interface timing among the bit clock, DATAL, and DATAR is required to meet the same setup and hold-time

specifications as shown for the PCM audio-format interface in Figure 36.

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