PCM1738ESLASH2K datasheet(33/47 Pages) TI2

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SYSTEM CLOCK (SCKI) AND INTERFACE TIMING

AUDIO FORMAT

FUNCTIONS AVAILABLE IN THE EXTERNAL DIGITAL-FILTER MODE

MSB

LSB

BCK

DATAL

DATAR

1/4f

or1/8f

WDCK

AudioDataWord=16-Bit

AudioDataWord=20-Bit

AudioDataWord=24-Bit

10 11 12 13 14 15

17 18 19

10 11 12 13 14 15

17 18 19

21 22 23

DATAL

DATAR

DATAL

DATAR

T0198-01

PCM1738

SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007

The external digital-filter application mode is available by programming the following bits in the corresponding

mode control registers:

DFTH = 1 (register 20)

DME = 0 (register 18)

The pins used to provide the serial interface for the external digital filter are shown in the application diagram of

Figure 41. The word (WDCK) and bit (BCK) clock signals, as well as the audio data inputs (DATAL and DATAR)

must be operated at 8

× or 4× the original sampling frequency at the input of the digital filter.

The PCM1738, in external digital-filter mode, allows any system-clock frequency synchronized with BCK and

WDCK. The system clock may be phase-free with BCK and WDCK. See Figure 43 for interface timing among

WDCK, BCK, DATAL, and DATAR.

In external digital-filter interface mode, the PCM1738 supports a right-justified audio format interface including

16-, 20-, and 24-bit audio data (see Figure 42) that should be selected by FMT[2:0] of mode control register 18.

The external digital-filter mode allows access to the majority of the PCM1738's mode-control functions. Table 5

shows the register mapping available when the external digital-filter mode is selected, along with descriptions of

functions that are modified for this mode selection.

Figure 42. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application

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