SCL

S

P

P

STO

condition

START condition

SDA

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

22

LM3555

SNVS594G – DECEMBER 2008 – REVISED APRIL 2016

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Copyright © 2008–2016, Texas Instruments Incorporated

7.5 Programming

7.5.1 I2C-Compatible Interface

7.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state

of the data line can only be changed when CLK is LOW.

Figure 41. Data Validity Diagram

A pullup resistor between VIO and SDA must be greater than (VIO – VOL) / 3 mA to meet the VOL requirement on

SDA. Using a larger pullup resistor results in lower switching current with slower edges, while using a smaller

pullup results in higher switching currents with faster edges.

7.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the I2C session. A START condition is

defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as

the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and

STOP conditions. The I2C bus is considered to be busy after a START condition and free after a STOP condition.

During data transmission, the I2C master can generate repeated START conditions. First START and repeated

START conditions are equivalent, function-wise. The data on SDA line must be stable during the HIGH period of

the clock signal (SCL). In other words, the state of the data line can only be changed when CLK is LOW.

Figure 42. Start and Stop Conditions

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM3555 pulls

down the SDA line during the 9th clock pulse, signifying an acknowledge. The LM3555 generates an

acknowledge after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). The LM3555 address is 30h. For the eighth bit, a 0 indicates a

WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third

byte contains data to write to the selected register.