L1

COUT

CIN1

CIN2

LM3555

7.0 mm

31

LM3555

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SNVS594G – DECEMBER 2008 – REVISED APRIL 2016

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10 Layout

10.1 Layout Guidelines

The DSBGA is a chip-scale package with good thermal properties. For more detailed instructions on handling

and mounting DSBGA packages, refer to AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009).

The high switching frequencies and large peak currents make the PCB layout a critical part of the design. The

proceeding steps must be followed to ensure stable operation and proper current source regulation.

1. Connect the inductor as close to the SW pin as possible. This reduces the inductance and resistance of the

switching node which minimizes ringing and excess voltage drops.

2. Connect the return terminals of the input capacitor and the output capacitor as close to the two ground pins

(PGND and SGND) as possible and through low impedance traces.

3. Bypass VIN with a 10-µF ceramic capacitor and an additional 0.1-µF ceramic capacitor. Connect the positive

terminal of this capacitor as close to VIN as possible.

4. Connect COUT as close to the VOUT pin as possible. This reduces the inductance and resistance of the output

bypass node which minimizes ringing and voltage drops. This improves efficiency and decreases the noise

injected into the current sources.

10.2 Layout Example

Figure 58. LM3555 Layout