LM27213

SNVS377A – FEBRUARY 2006 – REVISED MARCH 2013

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SOFT START

When VRON is enabled the regulator begins a normal start sequence that actively controls the rise of output

voltage. An internal 20µA current source supplies current through the Soft Start pin (25) that charges the soft

start capacitor. The output voltage is forced to track this voltage up. The result is a linear output voltage rise. The

capacitor value required is simply 20µA divided by the desired slew rate. For an output voltage rate of rise of

1V/ms, the capacitor should be about 20nF.

SOFT STOP

When VRON is deasserted, the LM27213 starts to discharge the soft start capacitor with an internal 45µA current

sink. Vcore is forced to follow the resulting linear ramp voltage on the soft start capacitor downward. When Vcore

reaches approximately 300mV the high-side FET is disabled and the low-side FET is turned on to quickly

discharge the output to zero and hold it there. This forces a controlled turn off slew rate that eliminates the

possibility of the output voltage ringing significantly below ground. It can also be helpful in the sequencing of

multiple supply rails.

STARTUP SEQUENCING

At initial power up the LM27213 targets a voltage equal to Vboot. This is the voltage level set at the VBOOT pin

(27) by a resistor divider that is powered by the V1R7 reference output (pin 26). This divider also has taps for the

OVP threshold and deeper sleep voltage set point. The regulator’s output will remain at Vboot until a time Tboot

after the XPOK flag clears. Tboot is nominally 20µs. After the Tboot time expires CLK_EN# will be asserted and the

output will transition to the voltage selected by the VID bits. Power good will be enabled nominally 5ms after

CLK_EN# is asserted.

DYNAMIC VID TRANSITIONS

Upon detecting a VID or mode change the LM27213 masks the power good comparator for a period of

approximately 130µs. During the blanking interval the power good output is forced high while the output voltage

is in slew to the newly selected level. The slew rate is determined by the soft start capacitor value. The

charge/discharge current driving the soft start capacitor will be 350µA typically. The programmed slew rate is

therefore 350µA divided by the soft start pin capacitance.

STOP CPU MODE

If the STP_CPU# pin (34) is asserted with SLP de-asserted the VREF pin voltage will be forced to the voltage on

the VSTP pin (32). The output will slew at a rate determined as above to the new value. The PGOOD mask is in

effect for 130µs.

SLEEP MODE

To enable sleep mode both STP_CPU# and SLP need to be asserted. The VREF pin voltage will transition to the

voltage on the VSLP pin with a slew rate as discussed under ynamic VID transitions and the PGOOD mask is

activated for 130µs.

POWER SAVING MODE

The LM27213 allows for high efficiency operation at very low power levels by employing a diode emulator mode.

This can be activated in either deep sleep or deeper sleep modes only. Assert the DE_EN# pin while in a sleep

mode to activate this function. When operating at low power the LM27213 detects inductor current reversal with a

zero cross detector connected to the drain of the low-side FET. The voltage at this node is normally below

ground when the low side FET is on but will become positive when the inductor current reverses. When the

inductor current reversal is detected the low side switch is turned off and essentially becomes a nearly ideal

diode. Due to the hysteretic control mode, the regulator operating frequency will be greatly reduced at light loads.

High-side switch on-time will not change significantly compared to normal operation, but the off times will extend

greatly. Care must be taken to connect the SRCK (Source Kelvin, pin 5) close to the low-side switch source

connection, as this is the reference input to the zero cross detector.

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