LM27213

SNVS377A – FEBRUARY 2006 – REVISED MARCH 2013

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Since the power plane resistance will increase the load line by an amount that’s nearly impossible to estimate

accurately, the simplest approach is to install the values calculated for the ideal, lossless power path, and run the

circuit. Record the no load and full load output voltage and calculate the load line impedance.

LL = (V0 – Vfull)/Ifull

where

•

V0 is the no load output voltage

•

Vfull is the full load output voltage

•

And Ifull is the full load current

(17)

Use this information along with the installed values of R1 and R2 to calculate the effective sense resistor value:

Rse = LL/(1+R1/R2)

(18)

Now using this value of sense resistor, recalculate a new value for R1:

R1 = R2(LL/Rse –1)

(19)

Installing these values for R1 and R2 should yield a nearly perfect load line.

Layout Guidelines

As is true for any high-current power supply design, care needs to be taken when doing an LM27213 layout. As

a general rule, it makes the most sense to start the layout by placing the power path components to connect in a

logical power flow. The input ceramic capacitors should be connected as close as physically possible to the

source of the low side FET and the drain of the high-side FET. The loop area enclosed by the input capacitors

and FETs needs to be minimized to control ringing and optimize the switch rise and fall times. A good practice is

to connect the FETs on the top side of the board with the bypass capacitors located immediately below on the

back side. The capacitors’ ground pads should be located directly beneath the low-side FET’s source pad and a

collection of vias used to hook the two together and at the same time tie to the internal ground plane. Figure on

allowing one amp of load current per via if the hole diameter is less than 15 mils and two Amps per via if greater

than 20 mils. More vias are almost always better than fewer.

Keep the switch node connection between the two FETs and the inductor as short and wide as possible. The

inductor should be located very close to the FETs. The inductor should then flow in to the sense resistor that

needs to be immediately adjacent to the processor decoupling capacitors.

The LM27213 needs to be located relatively close to the FETs to minimize the gate drive lengths. Also, route the

high-side gate signal (pin 2) and the SW pin (3) parallel to and very close to each other to minimize the

inductance of the loop enclosed. These traces should be at least 15 mils wide. The connections to the current

sense resistor must be made as Kelvin connections. Again, route these two traces in parallel if possible to

minimize noise susceptibility. The sense pin (16) is best connected to the core voltage near the center of the

CPU socket, but will in all likelihood work correctly if connected at the bypass capacitors located around the

periphery of the CPU socket. This line is the source of output voltage information for the over voltage protection

circuit and power good comparators.

Probably the most critical consideration for the controller is grounding. There are several ground-referenced pins

that need to be treated quite differently. A good practice is to tie the power ground pin (45) to the main power

plane with a single via. This pin is the ground connection for the gate drive and as such will carry very large

pulse currents. The bypass capacitor for DVDD should connect very close to this ground connection if at all

possible. DGND (13) is not particularly critical and should tie to the main ground plane as well. It only carries the

return currents for the digital portions of the controller, which are not very large. The SGND pin (23) is the most

critical and should also tie to the plane with a separate via close to PGND or directly to the PGND pin with a very

short trace. One grounding option is to define a signal ground plane that connects to ground through this point

only and resides under and around the IC. An alternative is to daisy chain a ground trace around the controller to

pick up all the signal ground referenced components while maintaining only a single connection to the ground

plane at the SGND pin. If doing the later and not defining signal ground as a separate net, it will not be possible

to use vias to connect to other layers unless your board layout package has the ability to isolate these vias from

the ground plane. Keeping the signal ground separate from the system ground plane ensures that signal ground

is “quiet” relative to all internal signals in the controller. The main ground plane is usually a very noisy

22

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