LM27213

SNVS377A – FEBRUARY 2006 – REVISED MARCH 2013

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In a similar fashion the high-side switch can be sized. Allot ½ of the total dissipation to switching losses. The on

interval is now DF rather than 1-DF and low input line is assumed:

Rds(on) = Pdiss/(I

2 x 1.4 x (DF))

(14)

Rds(on) = 0.25W/(9.6A

2 x 1.4 x 1.15V/8V)

•

Rds(on) = 13.4mΩ

(15)

An Si7390 high-side switch and an Si7336 low-side switch meet this requirement

If the same analysis is done assuming a 12A continuous load current the results suggest a low-side FET with an

on-resistance of 2.7m

Ω and a high-side FET on-resistance of 8.6mΩ.

GATE DRIVE REQUIREMENTS

The bootstrap capacitor choice is based largely on the gate charge requirements of the high-side FET. The

charge stored on the bootstrap cap should be about 20X the high-side FET’s gate charge. For the Si7390 the

specified gate charge is 15nC max. So the bootstrap capacitor should store a minimum of 300nC at 5V. This

translates to a capacitance of 0.06µF or larger. A 0.10µF or larger X5R dielectric capacitor would be a good

choice. Under sizing the bootstrap capacitor will result in inadequate gate drive to the high-side switch.

INPUT CAPACITOR SELECTION

The input capacitor selection is based largely on ripple current capability. The instantaneous pulse currents

drawn by the power supply must be deliv-ered by the input capacitors. This is related to the fact that the input

power source, be it a battery pack or a wall adapter, will place a substantial impedance in series with the input

path. As such, their ability to deliver large, fast rise time current pulses is limited. The input capacitors need to

average these pulse currents and smooth the current demand placed on the source.

Ceramic capacitors offer a good combination of ripple current capability and voltage rating, however they tend to

do so with relatively low capacitance values. It’s also not uncommon to find wall adapters and batteries with

impedances on the order of several hundred milliohms. The result is that while cycle-by-cycle current demand

may be met, the input capacitor network cannot deliver enough energy to prevent significant amounts of voltage

ripple when the load current is varied at a low rate. In particular, if the load varies at a frequency in the 2kHz to

4kHz range, the resulting large variation in voltage observed at the power supply input will result in noticeable

audio noise being produced by the piezo electric effects that are characteristic of ceramic capacitors. There are

several ways to mitigate this problem. The first is to use physically small ceramic capacitors since they tend to be

less efficient noise generators. That, however, would tend to limit the amount of capacitance to an unacceptably

low value. The use of aluminum-poly type capacitors such as Sanyo’s Poscap series is a viable option as well.

They can provide adequate levels of capacitance with very good ripple current capability. The down side of this

solution is cost. Another possible approach is to use relatively large ceramic capacitors and add a relatively large

aluminum electrolytic capacitor to hold up the supply voltage. The ceramics deliver the high frequency pulse

currents while the bulk caps smooth the longer term variation. In general a few hundred microfarads is adequate

for this purpose. As long as the AC ripple voltage impressed on the ceramic capacitors is small, on the order of a

few tenths of a volt, the ceramic capacitors are not going to be excessively noisy.

For purposes of sizing the high frequency input decoupling, the RMS input ripple current must be estimated. The

input ripple current will be approximately 50% of the output current at a 50% duty factor and decrease as duty

factor drops. Figure 22 shows this relationship.

20

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