ADS1610IPAPR datasheet(14/29 Pages) TI2

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REFERENCE INPUTS (VREFN, VREFP, VMID)

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

VREFP

VMID

VCAP

VREFN

392

Ω

OPA 2822

A DS1610

0.001

µF

392

Ω

OPA 2822

0.001

µF

392

Ω

OPA 2822

0.001

µF

2.5V

AGND

CLOCK INPUT (CLK)

ADS1610

VREFP

50pF

300

Ω

VREFN

VREFP

VREFN

ADS1610

SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006

The ADS1610 operates from an external voltage

reference. The reference voltage (Vref) is set by the

differential voltage between VREFN and VREFP: Vref

= (VREFP – VREFN). VREFP and VREFN each use

two pins, which should be shorted together. VMID,

approximately 2.5V, is used by the modulator. VCAP

connects to an internal node and must also be

bypassed with an external capacitor.

The voltages applied to these pins must be within the

values specified in the Electrical Characteristics

table. Typically VREFP = 4V, VMID = 2.5V, and

VREFN = 1V. The external circuitry must be capable

of providing both a DC and a transient current.

Figure 29 shows a simplified diagram of the internal

circuitry of the reference. As with the input circuitry,

switches S1 and S2 open and close as shown in

Figure 26.

Figure 30. Recommended Reference

Buffer Circuit

The ADS1610 uses an external clock signal to be

applied to the CLK input pin. The sampling of the

modulator is controlled by this clock signal. As with

Figure 29. Conceptual Circuitry for the Reference

any high-speed data converter, a high quality clock is

Inputs

essential for optimum performance. Crystal clock

oscillators are the recommended CLK source; other

Figure 30 shows the recommended circuitry for

sources, such as frequency synthesizers may not be

driving these reference inputs. Keep the resistances

adequate. Make sure to avoid excess ringing on the

used in the buffer circuits low to prevent excessive

CLK input; keeping the trace as short as possible will

thermal noise from degrading performance. Layout of

help.

these circuits is critical, make sure to follow good

Measuring high-frequency, large-amplitude signals

high-speed layout practices. Place the buffers and

requires tight control of clock jitter. The uncertainty

especially the bypass capacitors as close to the pins

during sampling of the input from clock jitter limits the

as possible.

maximum achievable SNR. This effect becomes

more pronounced with higher frequency and larger

magnitude

inputs.

The

ADS1610

oversampling

topology reduces clock jitter sensitivity over that of

Nyquist rate converters like pipeline and successive

approximation converters by a factor of

√6.

In order to not limit the ADS1610 SNR performance,

keep the jitter on the clock source below the values

shown in Table 1. When measuring lower frequency

and lower amplitude inputs, more CLK jitter can be

tolerated. In determining the allowable clock source

jitter, select the worst-case input (highest frequency,

largest amplitude) that will be seen in the application.

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