STW4810 datasheet(66/78 Pages) STMICROELECTRONICS

66 / 78 page

Electrical and timing characteristics

STw4810

66/78

5.6

SD/MMC card interface

Table 51.

SD/MMC card interface

Symbol

Description

Test conditions

Min.

Typ.

Max.

Units

VMMC regulator specifications (PDN_VMMC = 1)

VBAT

Input voltage

VOUT = 3 V

VOUT = 2.85 V

VOUT = 1.8 V

3.25

3.1

2.7

3.6

4.8

VOUT

Output voltage

-3%

2.85

1.8

+3%

IOUT

Output current

150

ISHORT

Short circuit

current limitation

280

360

600

Quiescent current

IOUT = 0 mA

µA

ILKG

Power-down

current

PDN_VMMC = 0

µA

PSRR(1)

Power supply

rejection

IOUT = 150 mA

Vpp = 0.3 V

f < 20 kHz

LIR

(1)

Line regulation

VOUT=2.85 V

VBAT: [3.1; 4.8]V

5mV

LDR

(1)

Load regulation

VOUT=2.85 V

IOUT= [1; 150] mA

LIRT

Transient line

regulation

VOUT=2.85 V

VBAT: 3.1 to 3.4V

tR = tF = 10 µs.

2mV

LDRT

Transient load

regulation

IOUT = [1; 150] mA

tR = tF = 1 µs

Settling time

OFF->ON

IOUT = 0 mA

100

µs

Discharge time

ON>OFF

IOUT = 0 mA

Bus line specifications

RA(2)

Pull-up resistor

To prevent bus

floating

1.5

Pull-down resistor

To prevent bus

floating

1.5

fDT

Clock frequency

data transfert

mode

With CL = 30pF

MHz

fID

Clock frequency

identification mode

With CL = 30pF

400

KHz

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