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STW4810 Datasheet(PDF) 37 Page - STMicroelectronics |
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STW4810 Datasheet(HTML) 37 Page - STMicroelectronics |
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37 / 78 page ![]() STw4810 Functional description 37/78 4.3.6 VAUX This LDO is dedicated either to the multimedia processor input/output signals or to the auxiliary devices. Power supply values are 1.5 V,1.8 V, 2.5 V, 2.8 V with 150 mA full load and 0.5 mA in sleep mode. In case of 1.5 V on the output, this LDO can be supplied by using VIO_VMEM DC/DC converter (1.8 V). One pad feed-back is used. Main features: ● Programmable output voltage, 4 levels (VAUX_SEL[1:0] bits of Power control register - Table 27) ● Three power domains: – ‘Normal mode’ when multimedia processor is in run mode, 150 mA full load – ‘Low current mode’ when multimedia processor is in sleep mode, 0.5 mA current capability. Fast switching from low current to normal mode. Note: Definition of sleep mode is given in 4.2.3: Sleep mode section. – ‘Power down mode’ or ‘standby mode’ when regulator is switched off, no power consumption (PDN_VAUX bit of SD MMC control register - Table 18) ● Default setting defined by start-up configuration 4.3.7 Power supply monitoring This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM drop below the threshold, the multimedia processor is reset. This feature can be desactivated by setting EN_MONITORING bit of Power control register ( Table 29) to “0”. 4.3.8 Power supply domains Table 29 lists the register bits that control STw4810 supply domains for each supply. Note: More details on VMMC supply are given in Section 4.5 Table 29. Power supply domains Supply name Description Supply domains Normal Sleep Power down VCORE STEP-DOWN 15 values VCORE_SEL[3:0] VCORE_SLEEP VCORE_FORCE_SLEEP EN_VCORE VIO_VMEM STEP-DOWN 1.8 V VIO_MEM_SLEEP VIO_VMEM_FORCE_SLEEP VPLL LDO 4 values VPLL_SEL[1:0] EN_VPLL VANA LDO 2.5 V EN_VANA VAUX LDO 4 values VAUX_SEL[1:0] VAUX_SLEEP VAUX_FORCE_SLEEP PDN_VAUX VMMC LDO 3 values SEL_VMMC[1:0] PDN_VMMC |
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