MB85R4M2T datasheet(3/25 Pages) RAMXEED

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DS501-00024-6v1-E

MB85R4M2T



PIN DESCRIPTIONS

Pin Number

Pin Name

Functional Description

1 to 5, 18 to 22,

23 to 27, 42 to 44

A0 to A17

Address Input pins

Select 262,144 words in FeRAM memory array by 18 Address

Input pins. When these address inputs are changed during /CE

equals to “L” level, reading operation of data selected in the

address after transition will start.

7 to 10, 13 to 16,

29 to 32, 35 to 38

I/O0 to I/O15

Data Input/Output pins

These are 16 bits bidirectional pins for reading and writing.

/CE

Chip Enable Input pin

In case the /CE equals to “L” level and /ZZ equals to “H” level,

device is activated and enables to start memory access.

In writing operation, input data from I/O pins are latched at the

rising edge of /CE and written to FeRAM memory array.

/WE

Write Enable Input pin

Writing operation starts at the falling edge of /WE.

Input data from I/O pins are latched at the rising edge of /WE

and written to FeRAM memory array.

/OE

Output Enable Input pin

When the /OE is “L” level, valid data are output to data bus.

When the /OE is “H” level, all I/O pins become high impedance

(High-Z) state.

/ZZ

Sleep Mode Input pin

When the /ZZ becomes to “L” level, device transits to the Sleep

Mode.

During reading and writing operation, /ZZ pin shall be hold “H”

level.

39, 40

/LB, /UB

Lower/Upper byte Control Input pins

In case /LB or /UB equals to “L” level, it enables

reading/writing operation of I/O0 to I/O7 or I/O8 to I/O15

respectively. In case /LB and /UB equal to “H” level, all I/O

pins become High-Z state.

11, 33

VDD

Supply Voltage pins

Connect all two pins to the power supply.

12, 34

VSS

Ground pins

Connect all two pins to ground.

Note: Please refer to the timing diagram for functional description of each pin.

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