12

DS501-00024-6v1-E

MB85R4M2T

3. Write Cycle Timing 1 (/WE Control)

4. Write Cycle Timing 2 (/CE Control)

t

CW

t

PC

t

AS

t

AS

t

CA

tWP

t

WZ

tWX

t

BS

t

BH

tWLC

* : In case the /OE is “L” level, any bus conflict of input and output data shall not occur.

t

AH

t

WHA

Valid Address

Valid Input Data

Invalid Output Data

I

nvalid Output Data

t

DS

t

DH

t

HZ

A0 to A17

I/O0 to I/O15

/CE

/WE

/LB, /UB

XXX : H or L

* : In case the /OE is “L” level, invalid data are output to data bus.

t

WC

t

CAH

t

CA

t

WS

t

PC

t

AS

t

AS

Valid Address

t

DS

t

DH

t

WH

t

BS

t

AH

Valid Input Data

/ LB, / UB

A0 to A17

/ CE

/ WE

I/ O0 to I/ O15

XXX : H or L

t

BH

t

WC

t

CAH