L9679ETR datasheet(76/127 Pages) STMICROELECTRONICS

76 / 127 page

High- and low-side FET diagnostics

This couple of tests can only be run during the diagnostic mode of the power-up sequence (as described in

Figure 6. IC operating state diagram). Tests are performed individually for HS driver or LS driver, with two

dedicated commands. Prior to either the HS or LS FET diagnostics being run, the VRCM has to be first enabled.

Within the command to enable the VRCM, also the channel onto which the FET test will be run has to be selected

with the LEAK_CHSEL bit field. Running the leakage diagnostics with the appropriate delay time prior to either the

HS or LS FET diagnostics will precondition the squib/pyroswitch pin to the appropriate voltage level. When the

FET diagnostic command is issued with the Diagnostic Register SPI command (SYSDIAGREQ), the VRCM flags

will be cleared, the VRCM deglitch filter time is switched from the leakage diagnostic deglitch filter time (TFLT_LKG)

to the FET test deglitch filter time (TFLT_LKGB_FT) for both HS and LS and the output of the VRCM deglitch filter is

now allowed to disable the appropriate HS or LS squib/pyroswitch driver during FET test.

The device monitors the current through the VRCM. If the FET is working properly, this current will exceed

IHS_FET_TH or ILS_FET_TH current threshold, respectively for HS or LS FET test for the deglitch filter time of

TFLT_LKGB_FT, and the driver under test is turned off immediately and automatically.

If there is a substantial leakage fault to Vbat or Gnd present during the FET test, leading this leakage current to

exceed the IHS_FET_TH or ILS_FET_TH current threshold, for the deglitch filter time of TFLT_LKGB_FT, then the

driver under test is turned off immediately and automatically, and the corresponding VRCM flag, STG or STB, is

set.

If the current does not exceed the current threshold, the test will be terminated and the driver is anyway turned off

within TFETTIMEOUT.

Table 12. HS FET TEST

VRCM Flags

Result

STG

STB

FET test fail

FET test pass

Leakage to Vbat

FET test disabled

due to Leakage to Gnd

State not possible

Table 13. LS FET TEST

VRCM Flags

Result

STG

STB

FET test fail

FET test disabledd

due to Leakage to Vbat

FET test pass

Leakage to Gnd

State not possible

During TFETTIMEOUT period, the bit stating that the FET is enabled will be set (FETON=1) and will be cleared as

soon as the FET is switched back off.

L9679E

Deployment drivers

DS12485 - Rev 8

page 76/127

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