L9679ETR datasheet(86/127 Pages) STMICROELECTRONICS

86 / 127 page

L9679E supports three time slots in a sync period with associated RSDRx registers. The messages received

within one sync period are routed to the corresponding RSDRx register associated to each time slot. A time slot

control is performed to check if the incoming messages fall within the valid time slots reported in Table 34. PSI-5

Satellite Transceiver - AC Specifications and sketched in Figure 25. PSI5 Slot Timing Control. If the end of the

received message occurs outside a valid time slot, a SLOT_ERROR fault will be detected and stored in the

related RSDRx register. Slot error assignment is described in Figure 25. PSI5 Slot Timing Control. For instance, if

the end of second message falls before expected valid time window the error slot 1 is asserted and then also the

data received with the first message is lost. If two messages end within the same slot, the second message will

be assigned to that slot, regardless of its validity. The time slot control can be disabled by setting the TSxDIS bit in

the RSCRx register.

Figure 25. PSI5 Slot Timing Control

GADG1203180749PS

Response

Receiver

Detect windows

Frame end

From Satellite

PSI5 frames

Vbase+0.5 V

Vbase

SATSYNC PIN

SYNC PULSE ENABLE

Error Slot 1

Slot 1

T_s1_end_open(max)

T_s1_end_open(min)

T_LS_1

T_ES_1

Slot 1

Valid

T_LE_1

T_EE_1

T_s2_end_open(max)

T_s2_end_open(min)

Error Slot 1

Slot 2

T_s1_end_closure(max)

T_s1_end_closure(min)

T_LS_2

T_ES_2

Slot 2

Valid

T_LE_2

T_EE_2

T_s2_end_closure(max)

T_s2_end_closure(min)

T_s3_end_open(max)

T_s3_end_open(min)

Slot 2

Error

Slot 3

T_LS_3

T_ES_3

Slot 3

Valid

T_EE_3

T_s3_end_closure(max)

T_s3_end_closure(min)

included

Stop bit not

Error Slot 3

T_LE_3

Asynchronous mode

For PSI-5 asynchronous mode, three data registers per channel are used to store a maximum of three remote

sensor messages.

In this way the frequency of SPI access of the microcontroller to read data can be reduced assuming that during

each phase of data reading the microcontroller is able to send consecutive SPI frames to read all accumulated

data.

This data buffer works as a FIFO, so the microcontroller reads always the oldest data message.

In case the microcontroller is not fast enough to read the three accumulated data, the IC will discard the oldest

data when new data is incoming.

SPI access to read data is asynchronous respect to writing of data registers, so the IC has been designed to

prevent data losses in case these two events occur at the same time.

There is only one SPI register address for each channel that the microcontroller has to read to get all the data.

This address is the one related to slot1 in the equivalent synchronous mode.

Trying to read addresses related to slot2 and slot3 will respond with all zeros in READ[19:16] field of MISO_RS.

L9679E

Remote sensor interface

DS12485 - Rev 8

page 86/127

L9679ETR Datasheet(PDF) 86 Page - STMicroelectronics

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