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L9679ETR Datasheet(PDF) 101 Page - STMicroelectronics |
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L9679ETR Datasheet(HTML) 101 Page - STMicroelectronics |
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101 / 127 page ![]() Table 26. SPI AC specifications Symbol Parameter Comments / Conditions Min Typ Max Unit FSCLK SPI transfer frequency - - 8 8.08 MHz tSCLK SCLK_x period - 123.8 - - ns tLEAD Enable lead time - 250 - ns tLAG Enable lag time - 50 - - ns tHIGH_SCLK SCLK_x high time (5) - 40 - - ns tLOW_SCLK SCLK_x low time - 40 - - ns tSETUP_MOSI MOSI_x input setup time - 20 - - ns tHOLD_MOSI MOSI_x input hold time - 20 - - ns tACC_MISO MISO_x access time 80 pF load - - 60 ns tDIS_MISO MISO_x disable time 80 pF load - - 100 ns tVALID_MISO MISO_x output valid time 80 pF load - - 30 ns tHOLD_MISO MISO_x output hold time 80 pF load Design info 0 - - ns tNODATA SCLK_x hold time - 20 - - ns tFLT_CS CS_x noise glitch rejection time - 50 - 300 ns tNODATA SPI Iinterframe time - 400 - - ns Note: All timings are shown with respect to 10% and 90% of the actual delivered VCC voltage. Figure 28. SPI timing diagram tHIGH_SCLK CS _ x SCLK _ x tLEAD tACC_MISO tSETUP_MOSI tHOLD_MISO tLOW_SCLK tVALID_MISO tSCLK MSB OUT tLAG tNODATA tNODATA tHOLD_MISO tDIS_MISO LSB IN DATA DATA LSB OUT DON’T CARE MSB IN MISO _ x MOSI _ x GADG1203181209PS L9679E Electrical characteristics DS12485 - Rev 8 page 101/127 |
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