D950-CORE datasheet(12/89 Pages) STMICROELECTRONICS

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D950-Core

Data buses (XD/YD and XA/YA) are provided externally. Data memories (RAM, ROM) and

peripherals registers are to be mapped in these address spaces.

Instruction bus (ID/IA) gives access to program memory (RAM, ROM). Each bus has its own

control interface

Table 3.1

Data/Instruction Bus and Corresponding Address Bus.

Depending on the calculation mode, the D950-Core DCU computes operands which can be

considered as 16 or 32-bit, signed or unsigned. It includes a 16 x 16-bit parallel multiplier able

to implement MAC-based functions in one cycle per MAC. A 40-bit arithmetic and logic unit,

including a 8-bit extension for arithmetic operations, implements a wide range of arithmetic

and logic functions. A 40-bit barrel shifter unit and a bit manipulation unit are included.

Tables 3.2 and 3.3 illustrate the different types of word length and word format available for

manipulation.

Table 3.2

Summary of Possible Word Lengths

Data / Instruction Buses

Corresponding Address Bus

Bidirectional

16-bit

Unidirectional

16-bit

Bidirectional

16-bit

Unidirectional

16-bit

Bidirectional

16-bit

Unidirectional

16-bit

01-bit word

8-bit word

16-bit word signed / unsigned

32-bit word signed / unsigned

40-bit word signed / unsigned

Table 3.3

Summary of Possible Word Formats

Format

Minimum

Maximum

fractional

signed

- 1

+ 0.999969481

unsigned

+ 0.99996948

integer

signed

- 32768

+ 32767

unsigned

+ 65535

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