D950-CORE datasheet(27/89 Pages) STMICROELECTRONICS

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D950-Core

Table 4.2

Interrupt Sources and Priority

RESET

Non maskable (internally vectorized), either hardware or software (see Table 6.3.3“Hardware

Reset”)

In hardware, when a low level is applied to the RESET input, the CLOCK generator is re-

synchronized, the PC is reset, execution of NOP instructions is forced and control registers are

initialized.

In order to get a valid reset, a low level must be applied for a minimum of ten CLKIN cycles (i.e

five D950-Core cycles).

In software, the RESET instruction is a 3-cycle instruction having the same effects as a

hardware reset, except the CLOCK generator is not re-synchronized.

The reset address is 0x0000. By setting the MODE pin to 1, the alternate reset address

0XFC00 is selected.

INT

Maskable external interrupt EI and IPE bits of STA register (see Table 6.3.5“Interrupt”)

Start of Interrupt: External interrupt is disabled on reset and is enabled by setting EI-bit to 1.

As soon as an IT falling edge is memorized and recognized by the PCU at the beginning of an

instruction cycle, IPE-bit is set. Provided IT has been previously enabled, ITACK signal is

asserted low to acknowledge the interrupt. ITACK stays at the low state for one cycle, allowing

the interrupt vector to be provided by the controller on Y-bus. Then IPE-bit is reset. Interrupt

start processing requires three cycles to read the interrupt vector and to fetch the

corresponding instruction. Meanwhile, CCR register, STA and the return address are

automatically saved onto the stack, located in X-memory space.

Return from Interrupt: Return from the interrupt is performed by the RTI instruction, a 3-cycle

instruction during which the return address, STA register and CCR are retrieved from the

stack. The EOI signal is then asserted low, allowing the controller to arbitrate pending interrupt

requests and to issue, if required, the next interrupt request to the D950-Core.

An interrupt request that is recognized while decoding or executing a delayed branch

instruction, is not acknowledged until all operations related to the branch have been

completed.

In addition to this external interrupt source, a powerful interrupt controller is available as

peripheral of the D950-Core (see Section 7.3).

Sources

Priority

RESET

Non-Maskable

Highest

SWI

Non-Maskable

INT

Maskable

Lowest

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