LM46002PWPRG4 datasheet(41/54 Pages) TI2

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LM46002

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SNVSA13C – APRIL 2014 – REVISED APRIL 2019

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Layout Guidelines (continued)

High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of

the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the

key to EMI reduction.

The SW pin connecting to the inductor must be as short as possible and just wide enough to carry the load

current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current

condution path to minimize parasitic resistance. The output capacitors should be place close to the VOUT end of

the inductor and closely grounded to PGND pin and exposed PAD.

Place the bypass capacitors on VCC and BIAS pins as close as possible to the pins respectively and closely

grounded to PGND and the exposed PAD.

10.1.2 Ground Plane and Thermal Considerations

TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for

sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The AGND and

PGND pins should be connected to the ground plane using vias right next to the bypass capacitors. PGND pins

are connected to the source of the internal LS switch. They should be connected directly to the grounds of the

input and output capacitors. The PGND net contains noise at the switching frequency and may bounce due to

load variations. The PGND trace, as well as PVIN and SW traces, should be constrained to one side of the

ground plane. The other side of the ground plane contains much less noise and should be used for sensitive

routes.

It is recommended to provide adequate device heat sinking by utilizing the PAD of the IC as the primary thermal

path. Use a minimum 4 by 4 array of 10 mil thermal vias to connect the PAD to the system ground plane for heat

sinking. The vias should be evenly distributed under the PAD. Use as much copper as possible for system

ground plane on the top and bottom layers for the best heat dissipation. It is recommended to use a four-layer

board with the copper thickness, for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer

boards with enough copper thickness and proper layout provides low current conduction impedance, proper

shielding and lower thermal resistance.

The thermal characteristics of the LM46002 are specified using the parameter RθJA, which characterize the

junction temperature of the silicon to the ambient temperature in a specific system. Although the value of RθJA is

dependant on many variables, it still can be used to approximate the operating junction temperature of the

device. To obtain an estimate of the device junction temperature, one may use the following relationship:

TJ = PD × RθJA + TA

where

•

TJ = junction temperature in °C

•

PD = VIN x IIN x (1 − Efficiency) − 1.1 × IOUT x DCR

•

DCR = inductor DC parasitic resistance in Ω

•

RθJA = junction-to-ambient thermal resistance of the device in °C/W

•

TA = ambient temperature in °C.

•

(27)

The maximum operating junction temperature of the LM46002 is 125°C. RθJA is highly related to PCB size and

layout, as well as enviromental factors such as heat sinking and air flow. Figure 101 shows measured results of

RθJA with different copper area on a 2-layer board and a 4-layer board.

LM46002PWPRG4 Datasheet(PDF) 41 Page - Texas Instruments

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