L99PM72GXP datasheet(37/129 Pages) STMICROELECTRONICS

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L99PM72GXP

Detailed description

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mode (SW_EN = 0) the automatic voltage biasing is disabled and the transceiver biasing

works according to ISO 11898-5.

There is no automatic state transition into TRX Normal Mode in case of a detected CAN

wake-up (WUF or WUP). After serving the interrupt the micro controller can initiate a state

transition into TRX Normal Mode by setting the SPI bit CAN_ACT to '1'.

TRX_SLEEP (SW_EN=1)

The CAN and LIN Transceivers are disabled. The CAN selective wakeup reference

oscillator is off, while the receiver is in low power mode.

After the detection of CAN communication (WUP), the transceiver enters

'PN_TRX_selective_sleep' mode, starts the oscillator and decodes the CAN frame.

'TRX_SLEEP' mode is entered automatically after a CAN communication timeout.

PN TRX Selective Sleep (SW_EN=1)

In this mode the CAN frame detection logic is enabled (receiver and reference oscillator

enabled). In case of receiving a wake up frame (WUF) a state transition to 'CAN

TRX_STBY' is done. After the biasing has been switched on, not more than four CAN

frames are ignored before a wake-up frame is recognized and the device wakes up.

If there is no CAN communication and the CAN bus is recessive for longer than tsilence, an

automatic state transition to 'TRX_SLEEP' is done.

In case of a Frame-Detect-Error (SR4, FDERR=1), an automatic wake up is performed and

the selective wakeup feature is disabled (SW_EN=0).

Oscillator monitoring

While selective wake-up is enabled, a timer is started with each recessive to dominant edge.

If after the expiration of 300 µs on this timer less than 6 recessive bits are counted, an

oscillator fail is detected and the osc_mon bit is set to '1'. Subsequently the device enters

wake-up mode according to ISO11898-5 (wake-up pattern wake-up).

2.9.2

Sequence for enabling selective wakeup

After power-on reset the selective wakeup feature is disabled.

The Configuration Registers 7 to 15 have to be read and verified by the microcontroller in

order to ensure a valid configuration. A read operation to Registers 7 to 15 is required to

allow enabling the selective wake-up feature (set SW_EN=1).

A valid read operation is indicated by the SW_RDxx bits in SR 4. The SW_RDxx bits are

reset to 0 with every WRITE operation.

When all SW_RD bits are set, the SW_EN bit in CR 16 can be set to enable the Selective

Wakeup function. In case the SYSERROR bit in SR 4 is set while Selective Wakeup is

enabled, the Selective Wakeup is automatically disabled. In case SYSERROR is set,

enabling the Selective Wakeup function is prohibited.

2.9.3

CAN error handling

The L99PM72GXP provides the following four error handling features.

L99PM72GXP Datasheet(PDF) 37 Page - STMicroelectronics

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