8

ECP5 Versa Development Board

®

On-Board Clock Capabilities

(See Appendix A, Sheet 9, Figure 18 - Reference Clock Generator)

The ECP5 Versa Development Board allows for several clock source options. Some of these options are controlled

via the ispClock5406D programmable clock manager device. The ispClock5406D enables the reference clock from

the PCI Express interface to provide a reference clock to the SERDES. This is true only when the board is in a PCI

Express host socket. When the board is not in a PCI Express host socket, the clock will be supplied by a 156.25

MHz clock on-board oscillator. Both clock inputs can be fanned out to the dedicated SERDES reference inputs,

FPGA inputs, and to the expansion connectors. The factory default programming only connects the SERDES refer-

ence clock inputs. Factory-defined demonstration designs will control and manage the clock.

Figure 6. Clock Controller Scheme

PCIE_PRSNT#

PCI Express

156.25 MHz

On-board

Oscillator

FPGA Clock

SERDES D0

Reference

Clock

SERDES D1

Reference

Clock

Expansion Interface

Clock(X3)

PCLKT0

A4

PCLKC0

A5

REFCLKP_D0

Y11

REFCLKN_D0

Y12

REFCLKP_D1

Y19

REFCLKN_D1

W20

Factory Default

Clock Programming

1

0