IMXRT1160AXEC datasheet(88/130 Pages) NXP

88 / 130 page

i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 4, 06/2025

NXP Semiconductors

Electrical characteristics

4.9.1

LPSPI timing parameters

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following tables provide timing

characteristics for classic LPSPI timing modes.

All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input

signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.

Figure 37. LPSPI Master mode timing (CPHA = 0)

Table 83. LPSPI Master mode timing

Number

Symbol

Description

Min.

Max.

Units

Note

fSCK

Frequency of operation

—

fperiph / 2

MHz

1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must guaranteed

this limit is not exceeded.

tSCK

SCK period

2 x tperiph

—

2 tperiph = 1000 / fperiph

tLead

Enable lead time

—

tperiph

—

tLag

Enable lag time

—

tperiph

—

tWSCK

Clock (SCK) high or low time

tSCK / 2 - 3

—

tSU

Data setup time (inputs)

—

tHI

Data hold time (inputs)

—

Data valid (after SCK edge)

—

tHO

Data hold time (outputs)

—

(OUTPUT)

MSB IN

LSB IN

MSB OUT

LSB OUT

(CPOL=0)

SCK

(CPOL=1)

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

1. If configured as an output.

PCS

(OUTPUT)

SOUT

(OUTPUT)

SIN

(INPUT)

BIT 6 . . . 1

IMXRT1160AXEC Datasheet(PDF) 88 Page - NXP Semiconductors

IMXRT1160AXEC Datasheet(HTML) 88 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL