DA9073 datasheet(57/134 Pages) RENESAS

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DA9073

Ultra-Low Quiescent Current PMIC

Datasheet

Revision 3.5

16-Jun-2023

57 of 134

DA9073

Host

SCL

MODE

ROUT_N

SYS_FLT

PWR_FLT

RIN_N

(always-on)

SDA

Figure 35: Digital Pin Connections

9.7.1

Watchdog Input and Timer

A programmable watchdog timer, WD, is available to detect a stall in the host. The WD function is

enabled or disabled at register 0x14:[1:0]. Each time the host initiates I2C or toggles the watchdog

input, the timer resets. If no host activity is detected within the timeout period, the DA9073 toggles

the SYS_FLT flag and sets the WD event bit at 0x07 to 1. If the register reset option is enabled, the

outputs are disabled for a period of typically 20msec and then re-enabled to reset the host. The

watchdog is automatically re-activated and the pre-programmed OTP values are loaded (except for

RIN_N_RST_ROUT_EN and RIN_N_RST_REC at register 0x10:[3:0]).

The watchdog timeout period is programmable to 25 or 50 seconds via the 0x14 register.

Optionally, the WD function can also toggle the ROUT_N pin, also selectable at register 0x14.

The WD_EN register selects when the watchdog timer is available as described in Table 35.

Table 35: WD_EN Register 0x14 [1:0]

Charge mode

Active battery mode

Hi-Z mode

0x0

Disable

0x1

Enable

Disable

0x2

Enable

Disable

0x3

Enable

The WD_CLR_SEL register selects which activity the WD uses to clear the timer, described in Table

36.

Table 36: WD_CLR_SEL Register 0x14 [3:2]

Description

0x0

Only I2C clears the timer

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