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DA9073 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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DA9073 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 134 page ![]() DA9073 Ultra-Low Quiescent Current PMIC Datasheet Revision 3.5 16-Jun-2023 11 of 134 © 2023 Renesas Electronics Table 1: Pin Description Pin No. Pin Name Type ( Table 2) Description A1, D3, F4 GND GND Ground connection. Connect to the ground plane A2 VDD_PWR POWER Input power supply. VDD_PWR is a 20 V-tolerant input. Bypass to GND with a minimum 1uF ceramic capacitor. A3, A4 VDD_SYS POWER VDD_SYS is the intermediate rail which typically supplies VDD_BUCK and VDD_BST. Bypass to ground with a 4.7 µF ceramic capacitor. A5 VDD_BUCK POWER Input of the buck converter. Bypass to PGND_BUCK with a minimum 2.2 µF ceramic capacitor. A6 SW_BUCK POWER Buck switching node. Connect to the buck inductor. A7 PGND_BUCK POWER Power ground for the buck. Connect to the buck input capacitor and ground plane. B1, B2 VBAT POWER Battery connection. Connect to the positive terminal of the battery. Bypass to ground with a minimum 1 µF ceramic capacitor. B3, D4, E4 NC B4 TEMP_SNS AI Battery Pack NTC monitor. Connect to a resistive network and thermistor. B5 SYS_FLT DOD Open drain status output. Connect to VDDIO through a 1 K to 100 KOhm pull-up resistor. B6 SDA DIO I2C Interface Data. Connect SDA to VDDIO through a 2 k to10 k pull-up resistor. B7 FB_BUCK AI Buck output voltage feedback connection. C1 VBAT_SNS AI Battery voltage sense connection. Connect to the positive battery terminal. C2 ITER_CHG AI Termination current setting pin. Connect a resistor between ITER_CHG and ground to set the pre-charge and termination currents (ITER). Alternatively, short this pin to ground to allow ITER to be programmed by register setting. C3 ILIM_CHG AI Fast-Charge current setting pin. Connect a resistor between ILIM_CHG and ground to set the fast-charge current (ICHG). Alternatively, short this pin to ground to allow ICHG to be programmed by register setting C4 WD DI Watchdog input. Toggle WD within the watchdog time-out period to avoid power reset. C5 RIN_N DI Manual reset input pin. RIN_N is internally pulled high. Pulling this pin low wakes the device from Ship Mode or performs a reset. C6 SCL DI I2C interface clock. Connect SCL to VDDIO through a 2 k to10 k pull-up resistor. C7 AGND GND Quiet ground connection. Connect to a quiet ground area. |
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