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DA9073 Datasheet(PDF) 61 Page - Renesas Technology Corp |
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DA9073 Datasheet(HTML) 61 Page - Renesas Technology Corp |
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61 / 134 page  DA9073 Ultra-Low Quiescent Current PMIC Datasheet Revision 3.5 16-Jun-2023 61 of 134 © 2023 Renesas Electronics Table 39: RIN_N Reset Timer Configuration Register Configuration Description RIN_N_RST_REC 0x10 [1:0] 0: RESET event has no effect 1: Enter ship mode at RESET 2: Enter Hi-Z mode at RESET PWR_CYC_MODE 0x12 [1] 0: Power-cycle triggered by VDD_PWR insertion / removal 1: Power-cycle triggered by RESET timer when VDD_PWR present RIN_N_RST_ROUT_EN 0x10 [3:2] 0: Disable ROUT_N toggle at RESET 1: Enable ROUT_N toggle at RESET 2: Enable ROUT_N toggle at RESET only when VDD_PWR is present The RIN_N timer can also be used to exit Ship mode. A WAKE1 event will trigger Ship mode exit, with WAKE2 and RESET being ignored. If ROUT_N is enabled, a RESET event will cause the ROUT_N output to toggle low for 400 msec (typ). ROUT_N is an open-drain output that should be pulled-up to the logic rail with a 1 k to 100 k resistor. |
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