AT45DB021E datasheet(67/68 Pages) RENESAS

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DS-AT45DB021E-8789 Rev. M

Page 67

5/16/24

AT45DB021E Datasheet

31. Revision History

Doc. Rev.

Date

Comments

8789A

05/2012

Initial document release.

8789B

11/2012

Corrected pinout diagrams to top view.

Added Read-Modify-Write section.

For figures Program Sector Protection Register, Read Sector Protection Register Command, and

Read Sector Lockdown Register Command, changed the opcode from n +15 to n +7.

Added note at end of section, Auto Page Rewrite.

Updated figure, Exit Ultra-Deep Power-Down.

In table, Additional Commands, changed “Auto Page Rewrite through Buffer” to “Auto Page Rewrite or

Read Modify Write through Buffer”.

Power-Up Timing, increased VPOR max from 1.55 to 1.60.

tXUDPD, 1.65 V increased maximum 70 µs to 120 µs and 2.3 V maximum from 70 µs to 240 µs.

tSE, increased typical from 250 ms to 350 ms and maximum from 450 ms to 550 ms.

Increased 1.65 V and 2.3 V typical and maximum values for IDPD, ISB, ICC1, and ICC2.

Added Legacy Commands table.

Updated datasheet status to preliminary.

Updated to Adesto template.

8789C

6/2013

Updated electrical and power specifications. Removed CCUN-T package from ordering codes, (not

available with this device).

Removed references to UBGA package (not available with this device). Moved “Buffer Read” from

Group C to Group A in Operation Mode Summary. Removed reference to concurrent read capability.

Removed preliminary datasheet status.

8789D

7/2013

Updated Auto Page Rewrite cycle to 50,000 cumulative page erase/program operations. Added

reserved part order codes.Updated DC conditions for VOL.

8789E

10/2013

Corrected Low Power Read Option (up to 15 MHz).

8789F

7/2015

Expanded explanation of Power up/Power down (Section 16). Added Die in Wafer Form package

option.Corrected the Read-Modify-Write description (Section 6.10). Removed unavailable package

and pin out diagram. Corrected Tables 15-6 and 15-7. Added information on Power Up (Section 16.1).

Updated Tables 12-1 and 12-3. Updated condition description for IUDPD, IDPD, and ISB. Updated Deep

Power Down and Ultra Deep Power Down timing diagrams.

8789G

3/2016

Added WLCSP package option. Updated Condition description for IDPD, and ISB. Added footnote to

tDIS, tEUDPD, tEPD.

8789H

1/2017

Added patent information.

8789I

7/2020

Updated format and layout. Copy edited throughout (no change in technical information).

For packages ending in SHN-B and SHN-T, removed link to note in the Ordering Codes tables that

states: “Not recommended for new designs. Use the 8S1 package option.”

8789J

3/2021

Updated notes to tables 28.2, 28.3, 28.4.

Removed original note 2 from table 28.3.

8789K

02/2022

Changed company logo to Renesas.

8789L

08/2022

Applied Renesas Corporate Template to document.

Added the following sentence to the description of CS in Table 1: “To ensure correct power-up

sequencing, it is recommended to add a 10k Ohm pull-up resistor from CS to VCC. This ensures CS

ramps together with VCC during power-up.”

8789M

04/2024

Changed note from below Table 34 from: “All inputs (SI, SCK, CS, WP, and RESET) are guaranteed by

design to be 5V tolerant.” to “All inputs (SI, SCK, CS, WP, and RESET) are guaranteed by design to be 5 V

tolerant; however, usage of 5V tolerance for extended periods can effect device reliability.”

Removed empty Section 32. Errata.

Updated/corrected the Ordering Information in Section 29.

Updated PODs in Section 30.

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