M7020R datasheet(88/150 Pages) STMICROELECTRONICS

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M7020R

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Table 39. Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, Up to 31 Devices

Table 40. Shift of SSF and SSV from SADR

272-bit SEARCH on Tables Configured as x272 Using a Single M7020R Device

The hardware diagram for this search subsystem

is shown in Figure 63, page 89. Figure 64, page 90

shows the timing diagram for a SEARCH com-

mand in the 272-bit-configured table (CFG =

10101010) consisting of a single device for one set

of parameters: TLSZ = ’00,’ HLAT = ’001,’ LRAM =

’1,’ and LDEV = ’1.’

The following is the sequence of operation for a

single 136-bit SEARCH command (also refer to

COMMAND CODES AND PARAMETERS, page

29).

– Cycle A: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair used for

bits [271:136] of the data being searched.

DQ[67:0] must be driven with the 68-bit data

([271:204]) to be compared to all locations “0” in

the four 68-bits-word page. The CMD[2] signal

must be driven to logic ’1.’

Note: CMD[2] = 1 signals that the search is a

x272-bit search. CMD[8:3] in this cycle is ig-

nored.

– Cycle B: The host ASIC continues to drive the

CMDV high and continues to apply the com-

mand code of SEARCH command ('10') on

CMD[1:0]. The DQ[67:0] is driven with the 68-bit

data ([204:136]) to be compared to all locations

“1” in the four 68-bits-word page.

– Cycle C: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair used for

bits [135:0] of the data being searched.

CMD[8:7] signals must be driven with the bits

that will be driven on SADR[21:20] by this de-

vice if it has a hit. DQ[67:0] must be driven with

the 68-bit data ([135:68]) to be compared to all

locations “2” in the four 68-bits-word page. The

CMD[2] signal must be driven to logic '0.'

– Cycle D: The host ASIC continues to drive the

CMDV high and applies SEARCH command

code ('10') on CMD[1:0]. CMD[8:6] signals must

be driven with the index of the SSR that will be

used for storing the address of the matching en-

try and the Hit Flag (see SEARCH-Successful

Registers (SSR[0:7]), page 23). The DQ[67:0] is

driven with the 68-bit data ([67:0]) to be com-

pared to all locations “3” in the four 68-bits-word

page. CMD[5:2] is ignored because the LEARN

Instruction is not supported for x272 tables.

Note: For 272-bit searches, the host ASIC must

supply four distinct 68-bit data words on

DQ[67:0] during Cycles A, B, C, and D. The

GMR Index in Cycle A selects a pair of GMRs

that apply to DQ data in Cycles A and B. The

GMR Index in Cycle C selects a pair of GMRs

that apply to DQ data in Cycles C and D.

# of devices

Max Table Size

Latency in CLK Cycles

1 (TLSZ = 00)

16K x 136-bit

2–8 (TLSZ = 01)

128K x 136-bit

9–31 (TLSZ = 10)

496K x 136-bit

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

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